Cross coverage of two covergroups

Hello All
I want to cross-coverage between two different covergroup, Is it possible to do this? Does SystemVerilog have this feature?

In reply to Malai_21:

No it does not have this feature. This is one of the top features I’m going to promote for the next revision.

Hi Dave
Is there any other way to implement this?

In reply to Malai_21:

Copy/paste :(

In reply to dave_59:

In reply to Malai_21:
No it does not have this feature. This is one of the top features I’m going to promote for the next revision.

Hi Dave,

Will you try also to promote the extension of covergroups/coverpoints when class is extend?
I mean adding ignores on some covergroups/coverpoints in inherited classes.
This is present in E(Specman) and found it to be very useful.
Or if you are familiar with other method or practice to achieve it in SV, would be happy if you can share it?

Thanks,
Michael

In reply to Michael54:

Yes both are on the list.

https://accellera.mantishub.io/view.php?id=2993
https://accellera.mantishub.io/view.php?id=2117

In reply to dave_59:

In reply to Michael54:
Yes both are on the list.
02993: Cross cover points across different cover groups - Accellera Mantis
02117: Allow extending of covergroups in classes - Accellera Mantis

Looks interesting, thank you for sharing :)

Dave when it is about to be released to us? Date announced?

Thanks,
Michael

In reply to Michael54:

2023 for release of the LRM. Tools may have already implemented some features.