Covergroup(with clock) defined in subscriber gives error

I have below covergroup. Since few coverpoints were not part of seq_item, I had to use them from interface. I used virtual interface in subscriber as below.
But i am getting error(test runs just for little time):
"

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ps Iteration: 10 Process: /tb_grp_ctrl_pkg::grp_ctrl_coverage::#grp_ctrl_chk#/Sample#(#grp_ctrl_chk#) File: …/…/tb_files/tb_grp_ctrl/tb_grp_ctrl_pkg.sv

Fatal error in file …/…/tb_files/tb_grp_ctrl/tb_grp_ctrl_pkg.sv

Fatal error reported during simulation. Cannot run ‘fcover’ command. Please look above output for the fatal error message(s). "

I just moved the same code to interface module and it all works fine showing 100% coverage. Any clue why it gives above error if its placed in subscriber?

 

class grp_ctrl_coverage extends uvm_subscriber#(grp_ctrl_seq_item);

  uvm_analysis_imp#(grp_ctrl_seq_item, grp_ctrl_coverage) trans_collected_export;
  grp_ctrl_seq_item grp_ctrl_trans;
  virtual grp_ctrl_if grp_ctrl_vif;

 covergroup grp_ctrl_chk @(posedge grp_ctrl_vif.clk);

    option.per_instance = 1;
    option.name = "GROUP CONTROL-2 coverage";
    grp_ctrl_cmd_cp : coverpoint grp_ctrl_trans.group_control_command { bins trans_0_1_0 = (0=>1=>0); }
    com_rd_addr_cp   : coverpoint grp_ctrl_vif.com_rd_addr {
                                        bins addr_bin[16] = {[0:15]};    }
  
     // check if, wr_en will have just one bit set corresponding to group number.
    awg_wr_en_cp      : coverpoint grp_ctrl_vif.awg_wr_en { bins b1[] = 25'h2,       25'h1 };                                      
    awg_wr_addr_cp   : coverpoint grp_ctrl_vif.awg_wr_addr {
                                      bins addr_bin[16] = {[0:15]};   }  
    awg_wr_en_addr_x : cross awg_wr_en_cp, awg_wr_addr_cp {ignore_bins bins_wr_cr = binsof(awg_wr_en_cp) intersect {'0} ;}                                 
  endgroup: grp_ctrl_chk
  
  function new(string name, uvm_component parent);
    super.new(name,parent);
    grp_ctrl_chk = new();
  endfunction : new

endclass 

In reply to uvmsd:

Are you sure grp_ctrl_vif is set before the first clock edge?

In reply to dave_59:

I think so, but not sure though. It all depends on whether, always or initial block gets executed first.

Below is what I have done in most of my TB top files. Though I have used grp_ctrl_vif.clk in driver, it never caused any problem since i wait for reset in driver.

In the top file, clk generation and vif setting is as below:

 module tb_grp_ctrl_top;   
  bit clk;
 
  //clock generation
  always #5 clk = ~clk;
  :
  :
  :
  initial begin
    uvm_config_db#(virtual grp_ctrl_if)::set(uvm_root::get(),"*","grp_ctrl_vif",intf);
  end
   :
   :
endmodule

And in the required subscriber, its accessed in build phase.

 function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    trans_collected_export = new("trans_collected_export", this);
    if(!uvm_config_db#(virtual grp_ctrl_if)::get(this, "", "grp_ctrl_vif", grp_ctrl_vif))
      `uvm_fatal("NO_VIF",{"virtual interface must be set for: ",get_full_name(),".grp_ctrl_vif"});
  endfunction : build_phase 

In that case, interface is the right place for these coverpoints, right?

Thank you!