Coverage not working

Coverage
1

hii guys , this is my coverage collector , but it is not hitting any of the bins , even if i give all the values to A and B , can you please tell the error in it

`ifndef ALU_COVCOL
`define ALU_COVCOL

class alu_covcl extends uvm_component;
`uvm_component_utils(alu_covcl)
alu_trans trans ;
 uvm_analysis_imp#(alu_trans, alu_covcl) imp_port;
virtual alu_interface vif; 


 
 function void write(alu_trans trans);
     cg_one_A.sample();
	 cg_one_B.sample();
	 cg_one_opcode.sample();
	
	cases.sample();
 
   `uvm_info(get_name() , $psprintf("RECEIVED Transaction : %s",trans.sprint()) , UVM_LOW);
 endfunction 
 
 
 covergroup cg_one_A ();
 
    cp_A: coverpoint vif.tb_mon.cb_tb_mon.A {
	bins A_min = {8'h0};
	bins A_max = {8'hFF};
	bins A_low = { [8'h0 : 8'h32]};
	bins A_inbet_low_medium = { [8'h33 : 8'h64]};
	bins A_medium = { [8'h65 : 8'h96]};
	bins A_inbet_medium_high = { [8'h97 : 8'hC8]};
	bins A_high = { [8'hC9 : 8'hFF]};
	}
endgroup

covergroup cg_one_B ();	
  cp_B: coverpoint vif.tb_mon.cb_tb_mon.B {
	bins B_min = {8'h0};
	bins B_max = {8'hFF};
    bins B_low = { [8'h0 : 8'h32]};
	bins B_inbet_low_medium = { [8'h33 : 8'h64]};
	bins B_medium = { [8'h65 : 8'h96]};
	bins B_inbet_medium_high = { [8'h97 : 8'hC8]};
	bins B_high = { [8'hC9 : 8'hFF]};
	}
endgroup

	
covergroup cg_one_opcode ();	 
  cp_opcode: coverpoint vif.tb_mon.cb_tb_mon.opcode  {
	bins unsigned_opcode = { [3'h0:3'h3]};
	bins logical_opcode  = {[3'b100:3'b101]}
    ignore_bins ignore = {[3'h6:3'h7]};
	}
endgroup 
	
	covergroup cases ;

 cp_add_B_zero_A : coverpoint (vif.tb_mon.cb_tb_mon.A==0 && vif.tb_mon.cb_tb_mon.B==0 && ( vif.tb_mon.cb_tb_mon.opcode inside {3'b000}))  {
      bins add_A_B_0 = {1'b1};
   }
   
 cp_Sub_B_grt_A : coverpoint (vif.tb_mon.cb_tb_mon.B > vif.tb_mon.cb_tb_mon.A) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b001})  {
      bins sub_A_grt_B = {1'b1};
   } 
   
 cp_Sub_B_eql_A : coverpoint (vif.tb_mon.cb_tb_mon.A == vif.tb_mon.cb_tb_mon.B) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b001})  {
      bins sub_A_eql_B = {1'b1};
   }   
 cp_Mul_B_zero_A : coverpoint (vif.tb_mon.cb_tb_mon.A==0 && vif.tb_mon.cb_tb_mon.B==0) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b010})  {
      bins Mul_A_B_0 = {1'b1};
   }     
 cp_Div_B_zero_A : coverpoint (vif.tb_mon.cb_tb_mon.A==0 && vif.tb_mon.cb_tb_mon.B==0) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b011})  {
      bins Div_A_B_0 = {1'b1};
   } 

 cp_logicaland_B_zero_A : coverpoint (vif.tb_mon.cb_tb_mon.A==0 && vif.tb_mon.cb_tb_mon.B==0) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b100})  {
      bins logicaland_A_B_0 = {1'b1};
   }
 cp_logicalor_B_zero_A : coverpoint (vif.tb_mon.cb_tb_mon.A==0 && vif.tb_mon.cb_tb_mon.B==0) && (vif.tb_mon.cb_tb_mon.opcode inside {3'b100})  {
      bins logicalor_A_B_0 = {1'b1};
   }       

endgroup

 
  function new(string name = "alu_covcl",uvm_component parent);
     super.new(name,parent);
	 
		cg_one_B=new();
		cg_one_opcode=new();
		
		cg_one_A=new();
		cases =new();

  endfunction
  function void build_phase (uvm_phase phase);
   `uvm_info(get_name() , "IN BUILD PHASE" , UVM_LOW)
   super.build_phase(phase);
      if(!uvm_config_db#(virtual alu_interface)::get(this, "*", "vif", vif))
       `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
 endfunction 
 endclass
 `endif //ALU_COVCOL
2

In reply to mittal:

There’s nothing obviously wrong with your covergroup. Can you print the value of vif.tb_mon.cb_tb_mon.A when sampling?

3

In reply to dave_59:

yes i can sample that but the issue is that , my coverage % is always zero , no matter if i give direct bins value . no bins is hitting or covergroup is not sampling

4

I think issue is you forgot to add below line in function new().

imp_port = new("imp_port",this);