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Coverage
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Coverage model for an array

Coverage 570
#coverage 57 #coverage #exclusion 3 #SystemVerilog ... 41
bachan21
bachan21
Full Access
118 posts
February 13, 2021 at 2:55 am

How we create a coverage model for an array for following problem statement?

Quote:
I have a 32 bit sized array of depth 1024. I want to check for the array elements from 0 to 767 that bins are covering values 100-2023. Array elements from 768-999 are illegal to access.
Rest of the elemental access must be excluded from coverage.

How can I put this into coverage model.

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dave_59
dave_59
Forum Moderator
11444 posts
February 13, 2021 at 11:13 pm

In reply to bachan21:

There is no sample timing in what you described. And you only have 768 elements. How are they supposed to be spread over 1924 values? If I were to model exactly what you wrote:

bit [31:0] array[1024];
 
covergroup cg with function sample(bit[31:0] element);
 coverpoint cp {bins b[1924] = { [100:2023] }; }
endgroup
 
cg cg_inst = new;
 
for(int i=0;i<768;i++). cg_inst.sample(array[i]);

You would never get 100% coverage.

— Dave Rich, Verification Architect, Siemens EDA

bachan21
bachan21
Full Access
118 posts
February 14, 2021 at 12:47 am

In reply to dave_59:
Lets say the sampling happens at rising edge of each clock.

You have covered the problem of covering array elements from 0 to 767.
But the solution does not include other part of the problem statement, i.e. mentioning elements at indices from 768 to 999 as illegal in coverage model.

Solution

Solution

dave_59
dave_59
Forum Moderator
11444 posts
February 14, 2021 at 10:36 am

In reply to bachan21:

So far you've only told me that you have an array, and I've shown you how to cover values in the elements inside that array. I have no idea how you access each element unless you explain the protocols used to access that array. How is an illegal access supposed to be represented?

In any case using a covergroup is not the best place to check for illegal behavior. You should be using assertions or something like that.

— Dave Rich, Verification Architect, Siemens EDA

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