why we need functional coverage? why code coverage is not enough to verification?
In reply to AKASHNBHAGAT:
There are two key reasons:
[1] For code coverage every design is just a RTL Verilog code. It does not distinguish between the processor or network switch design. So if you want to cover the design intent like instructions of processor or packets switch you need the functional coverage
[2] Code coverage does not address the concurrency, combinations and sequences. Its only addressed by functional coverage
Google “code coverage pain points” for more information on this topic.
In reply to AKASHNBHAGAT:
Code coverage is necessary, but not sufficient. Code coverage tells you your code has been exercised by a test. but says nothing about the correctness of code or the test for that matter.
Functional Coverage is a way of tracing the fact that your test has exercised a set of requirements and that those requirements have been met.
In reply to harinathdigital@gmail.com:
The point of RTL Verification is to catch as many hardware bugs as you can as soon as you can. The cost of fixing bugs goes up the longer it takes to find the bug. So “Coverage” is a set of metrics used to reduce the potential that there are outstanding bugs in your design.
In reply to harinathdigital@gmail.com:
Add to Dave’s point on cost of fixing bugs, Pentium FDIV bug which is one of the famous bugs costed 475 Million to fix. It could have been prevented by simple functional coverage on all the locations of the LUT table used inside the design.