Cover property syntax

Coverage
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1

Hello,

I’m new with System Verilog Assertion (SVA) and I get blocked with this synatx. Can anyone please explain to me the utility of “1’b1 ##1” in this cover property?
cover property ( @(posedge clk_bus)1’b1 ##1 tc_wdata != $past(tc_wdata) );

Thank you in advance.

2

In reply to hamza:

This moves the first comparison away from the first clock edge so there is no comparison with the default initialization value of tc_wdata. BTW a slightly simpler way to write this is

cover property ( @(posedge clk_bus) 1'b1 ##1 $changed(tc_wdata) );
3

In reply to dave_59:

Thank you Dave.

4

In reply to dave_59:

Hello Sir,

can you please explain to me what is mean by the zero after the same cycle implication “|-> 0” in this property :

$rose(req[0]) ##1 (~gnt[0] throughout (gnt[1])[->1]) |-> 0;

Thank you in advance.

5

In reply to hamza:

It means if the sequence on the LHS(antecedent) occurs, then fail.

I assume this was in an assert, not a cover directive.

6

In reply to dave_59:

Thank you Sir.
Yes it’s in an assert I just wanted to ask you directly .