Hi All,
I want to make a code to show code coverage for ternary operator.
module sv3vm_top;
reg a; wire y;
sv3vm sv3vm_inst(a,y);
initial
begin
a=0;
#2 a=1;
#2 a=0;
end
endmodule
module sv3vm(input a, output y);
assign y = a ? 1'b0: 1'b1;
endmodule
Commands to run
vlog -sv sv3vm.sv;
vopt sv3vm_top -o sv3vm_top_opt +acc +cover=bcesxf;
vsim sv3vm_top_opt -coverage;
Question -
- I am getting code coverage only for initial block. I want to get code coverage hit for assign y = a ? 1’b0: 1’b1;
But it’s not getting hit. I am using QuestaSim.
Please help as I am in starting of learning phase of code coverage.
Thanks,
R.Dave