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Coverage
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Code Coverage

Coverage 432
stf.cpll
stf.cpll
Full Access
2 posts
January 18, 2021 at 9:38 am

Hello,

I am new to verification and I have a question relating code coverage intended as a "measurement of structures within the source code that have been activated during simulation."

So far, I noticed that it is the simulation tool that automatically collects data about code coverage (like ModelSim/Questa "-cover" option), i.e. number of branches/conditions/expressions/etc.. that have been activated, and returns detailed info about hits and misses.

However, I am currently dealing with a simulator that does not have such built-in functionality.

So, is there a SystemVerilog construct or UVM class that I can use to achieve same result of collecting such overall code coverage, without having to individually spell out every element of the design in a separate covergroup?

Thank you

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dave_59
dave_59
Forum Moderator
8757 posts
February 03, 2021 at 10:35 pm

In reply to stf.cpll:

Theoretically you could use the VPI to instrument callbacks on every single executable line. can collect hit counts and then generate the reports yourself. But I've got to believe that any simulator that implements enough of the VPI to do this would already have code coverage built-in.

— Dave Rich, Verification Architect, Siemens EDA

stf.cpll
stf.cpll
Full Access
2 posts
March 02, 2021 at 1:02 pm

In reply to dave_59:

Hi Dave,

Thank you for your answer. I am using Xilinx Vivado.
Since I found that no easy solution existed involving VPI, I went about another route.

I created a python tool that works as source code parser, resolving compile-time defines across the design, evaluating parameters and generate statements.
Once that is done I reconstruct branches, conditions and expressions.
Branches (whose conditions are flattened and any nests tracked) are associated to a coverpoint each.
Conditions and expressions are covered with crosspoints by crossing the signals and logical comparisons that form them.

It was a month's work and it is not equivalent to a commercial solution, but it does provide some metrics and confidence over the design. Hopefully Xilinx will eventually release some code coverage built-in solution.

Thanks

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