I am new to verification and I have a question relating code coverage intended as a "measurement of structures within the source code that have been activated during simulation."
So far, I noticed that it is the simulation tool that automatically collects data about code coverage (like ModelSim/Questa "-cover" option), i.e. number of branches/conditions/expressions/etc.. that have been activated, and returns detailed info about hits and misses.
However, I am currently dealing with a simulator that does not have such built-in functionality.
So, is there a SystemVerilog construct or UVM class that I can use to achieve same result of collecting such overall code coverage, without having to individually spell out every element of the design in a separate covergroup?