Can we pass macro as argument to covergroup

hi,

is it possible to pass macro (`define ) to covergroup as argument ??

thanks
sandeep k

Macros are processed before the SystemVerilog source is parsed. So whatever the resulting expanded text of the macro is what gets passed as the argument to the covergroup.

In reply to dave_59:

thanks dave for ur reply, can u please give example for it…

or
here is my requirement

`define ABC 12,13

module new1
int a,b,c
covergroup xyz (int x, define ) //i dont know how to pass the above define to it(whether //as string or as int) { 1:coverpoint c { bins first = {ABC};
}
}

In reply to sandeep_kondle:

You can’t pass a macro name as an argument. The compiler will expand the text of the macro before it knows that the macro is being used as an argument to a covergroup.

There are two things you can do to get the functionality you seem to be looking for.

You can nest macro calls

`define mycg(name,binlist) covergroup name(int x);\
coverpoint c { \
  bins first = { binlist };\
} \
endgroup

`define ABC 12,13
module new1
int a,b,c;
`mycg(xyz,`ABC)

This expands to

module new1
int a,b,c
covergroup xyz(int x);
coverpoint c { 
  bins first = { 12, 13 };
} 
endgroup

Another thing you can do is use a new 1800-2012 feature that allows you to dynamically build arrays of bin values (supported by Questa 10.2).

const int ABC[] = {12, 13};
covergroup xyz(int binlist[]);
coverpoint c { 
  bins first = binlist;
}

xyz cg;

initial cg = new(ABC);

See http://go.mentor.com/ready-for-systemverilog-2012 for more details.

In reply to dave_59:

thanks dave for ur valuable solution…