Can we create a covergroup that can be instantiated number of times based on the number of channels we use?

To elaborate, can we add a parameterized trigger condition and cover point for coverage ?

psuedo code:

covergroup CG(bit condition, bit [2:0] cp1) @(posedge clk iff condition);
CP: coverpoint cp1
{
bins = {[0:3]};
}
option.per_instance = 1;
endgroup

logic [1:0] condition;
logic [2:0] signal1[1:0];

CG CG_inst_0 = new(condition[0], signal1[0]);
CG CG_inst_1 = new(condition[1], signal1[1]);

can we do this ?

In reply to aksistla:
You can accomplish what you want in SystemVerilog, however there are several thing to note about your pseudo code.

Arguments that will change value during the life of the covergroup and those changes need to seen inside the covergroup need to be passed by reference (the same is true with a task call).

covergroup CG(ref bit condition, bit [2:0] cp1) @(posedge clk iff condition);

Both condition and cp1 will now be passed by reference.
The iff construct in a covergroup, coverpoint, or bins construct does not control the existence of an instance of a covergroup, coverpoint, it only gates the sampling of the bins.

Finally, try to use arrays instead of naming individual instances inst_0, inst_1.

In reply to dave_59:

Hello Dave,

Thank you for the instant reply.

I tried to use the ref keyword and i am getting an error.
** Error: The select “req_in[0]” into a packed value is illegal for use with ref argument “condition”

Here I am passing an argument req_in[0] which is declared as logic [3:0] req_in;

Also, can i create arrays of covergroups in module ?

In reply to aksistla:
Is it possible to change the declaration to

 logic req_in[3:0];

Otherwise you will have to change the covergroup to

covergroup CG(input int index, ref bit [3:0] condition, bit [2:0] cp1) @(posedge clk iff condition);

and then pass 0,req_in to the covergroup’s constructor.