Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • CDC+RDC Analysis - 4/20
      • Low Power Verification - 4/29
      • User2User - 5/26
      • Webinar Calendar
    • On-Demand Webinars

      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • Questa Static and Formal Apps
      • All On-Demand Webinars
    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings
    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us
    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
Ask a Question
Coverage cross coverage
  • Home
  • Forums
  • Coverage
  • Forums: Coverage

Forums: Coverage

Primary tabs

  • Active
  • Solutions
  • Replies
  • No Replies
  • All(active tab)

14 questions in Coverage

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • Way to implement cross coverage so that 1 hit in the cross is considered to be covered.
    1  
    109  
    3 weeks 4 days ago
    by Nimisha Varadkar  
    3 weeks 4 days ago
    by dave_59  
  • Cross coverage of two covergroups
    7  
    335  
    3 months 6 days ago
    by Malai_21  
    4 days 9 hours ago
    by dave_59  
  • Sampling Cross Products Even when One Of The Cross_item Is Unknown/High Impedence.
     
    112  
    4 months 1 week ago
    by acidrainq  
    4 months 1 week ago
    No activity yet  
  • How to use struct member in cross coverage bin select expression
    1  
    208  
    6 months 3 weeks ago
    by marver22  
    6 months 3 weeks ago
    by dave_59  
  • cross coverage of two covergroups
    2  
    489  
    1 year 1 month ago
    by to_learn_uvm  
    1 year 1 month ago
    by dave_59  
  • cross coverage across multiple covergroup
    2  
    763  
    1 year 2 months ago
    by tsb_matumoto  
    1 year 2 months ago
    by tsb_matumoto  
  • Cross coverage with combination
    1  
    880  
    2 years 6 months ago
    by VENKATA_SRINIVAS  
    2 years 6 months ago
    by dave_59  
  • Unable to ignore automatic bins
    3  
    1,134  
    2 years 7 months ago
    by sj1992  
    2 years 7 months ago
    by dave_59  
  • How to define a generic cross coverage for generic range between two variables
    1  
    908  
    2 years 11 months ago
    by ravitejatelugunta  
    2 years 11 months ago
    by dave_59  
  • matches in cross coverage bin
     
    1,236  
    4 years 10 months ago
    by sharat  
    4 years 10 months ago
    No activity yet  
  • ISSUE WITH CROSS COVEPOINT
    3  
    1,514  
    6 years 4 months ago
    by samir singh  
    6 years 4 months ago
    by Tudor Timi  
  • Cross coverage issue when using -master option while merging UCDBs
     
    1,412  
    6 years 7 months ago
    by karthik.jagd  
    6 years 7 months ago
    No activity yet  
  • Trying to automate the generation of coverpoints, but I don't see any methods for higher level constructs in covergroups or crosses.
    1  
    1,489  
    7 years 2 weeks ago
    by etuers  
    7 years 2 weeks ago
    by dave_59  
  • Cross coverage of two covergroups
    9  
    9,503  
    7 years 2 weeks ago
    by Meeta  
    7 years 2 weeks ago
    by Meeta  

13,812 Questions

41,421 Replies

70,745 Users

Welcome to the Verification Academy Forums.

The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions.

We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

Important Links

  • Ask a Question
  • Use Code Tags
  • Forum FAQ
  • Forum Search
  • Forum Subscriptions

Forum Reminders

Do NOT begin your question with a "dot" (.do script).
Do NOT ask single word questions. Be specific!
Do NOT ask tool questions. Contact your tool vendor directly for support!


To help prevent Forum spam, your first question asked will be moderated.

Subscribe to Forums: Coverage

Available Forums

  • UVM
  • OVM
  • SystemVerilog
  • Coverage
  • Downloads
  • Announcements

Forum Tags

  • #SystemVerilog ... 31
  • #coverage 26
  • coverage 19
  • coverpoint 16
  • cross coverage 14
  • #systemverilog 13
  • functional coverage 12
  • covergroup 12
show all tags
Ask a Question
Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy