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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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      • Occurrence Property Patterns
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
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      • Register Abstraction Layer
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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      • RISC-V Design - Webinar
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      • The Three Pillars of Intent-Focused Insight
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    • Conferences & WRG

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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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Coverage
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539 questions in Coverage

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • How to get array of coverpoints
    15  
    21,759  
    9 years 11 months ago
    by prasads  
    2 days 20 hours ago
    by boss8032  
  • System Verilog coverage
    5  
    121  
    6 days 20 hours ago
    by dyno  
    3 days 17 hours ago
    by dave_59  
  • null object error
    1  
    42  
    1 week 5 days ago
    by Vrajesh_Rojivadiya  
    1 week 5 days ago
    by dave_59  
  • Adding ignore bin to Cross of a Cross
    3  
    68  
    2 weeks 2 days ago
    by sriram_6869  
    2 weeks 1 day ago
    by dave_59  
  • How to know about which seed is running and getting randomize when my seed is processed randomly ?
    3  
    71  
    2 weeks 3 days ago
    by chirag.hadiya  
    2 weeks 2 days ago
    by cgales  
  • creating bins for only even numbers
    4  
    6,180  
    8 years 6 months ago
    by Ranjitha YP  
    4 years 8 months ago
    by kumar-vin  
  • Functional Coverage for multiple monitors
    1  
    55  
    1 month 1 day ago
    by sonal112  
    1 month 1 day ago
    by cgales  
  • Working of option.per_instance
    5  
    12,455  
    4 years 6 months ago
    by Etrx91  
    1 month 3 days ago
    by qkuang  
  • How to exclude bins which are getting created automatically?
    2  
    110  
    1 month 6 days ago
    by Abuzar Gaffari  
    1 month 5 days ago
    by dave_59  
  • Command for exclude any line from code in code coverage.
    1  
    49  
    1 month 6 days ago
    by karan2969  
    1 month 6 days ago
    by cgales  
  • option.comment and type_option.comment
    1  
    89  
    1 month 2 weeks ago
    by m_v  
    1 month 2 weeks ago
    by dave_59  
  • COVERAGE ANALYZE
    1  
    79  
    1 month 3 weeks ago
    by Nandakumari  
    1 month 3 weeks ago
    by cgales  
  • Functional coverage
    1  
    98  
    1 month 3 weeks ago
    by saisrujan  
    1 month 3 weeks ago
    by dave_59  
  • coverges implicit bins
    1  
    134  
    2 months 5 hours ago
    by Prudhvi Krishna  
    2 months 1 hour ago
    by cgales  
  • How to write the functional coverage for SRAM 1KB, 4KB, 8KB, 16KB and 1MB?
    1  
    121  
    2 months 6 hours ago
    by shravan.v  
    1 month 4 weeks ago
    by dave_59  
  • How many bins are created and bins are covered, Here the percentage is 43.750000%? and why?
    6  
    242  
    2 months 1 week ago
    by shravan.v  
    2 months 6 days ago
    by shravan.v  
  • Why the assertion happens but its pass count is zero in the coverage result?
    1  
    238  
    3 months 1 week ago
    by Robert G  
    3 months 1 week ago
    by dave_59  
  • How to create the cover group's bins that based on array's values
    6  
    369  
    4 months 22 hours ago
    by faigenboim  
    3 months 3 days ago
    by faigenboim  
  • Disabling auto bins
    4  
    289  
    3 months 1 week ago
    by Hrithik_8050  
    3 months 1 week ago
    by Hrithik_8050  
  • How can I quantify the coverage in scenario verification?
    1  
    166  
    3 months 3 weeks ago
    by Lily_y  
    3 months 2 weeks ago
    by dave_59  

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16,862 Questions

50,986 Replies

90,147 Users

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