Web Seminar Series featuring the Verification Methodology Cookbook.
The Verification Methodology Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM, OVM and Coverage.
This series of online seminars, will focus on a featured monthly “recipe” guiding users into a deeper understanding of the material.
Web seminar recipes include:
- Beyond UVM: Effectively Modeling and Analyzing Coverage
This archived web seminar will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage, and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret. From there, we will review several examples that illustrate effective functional coverage for various applications, including bus protocol coverage, register-based block-level coverage and datapath coverage.
- C Based Stimulus for UVM
This seminar describes a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents. The approach used is to add a C register read/write API for use by C source code, which calls tasks in a SystemVerilog package via the SystemVerilog DPI mechanism to enable the C to make register accesses via the UVM testbench bus agents.
- Scoreboards and Results Predictors in UVM
If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a "golden" model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT. This online webinar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
- UVM Debug
UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, "Better Living Through Better Class-Based SystemVerilog Debug") and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
- UVM Connect
UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment.
- Introducing UVM Express
UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. Unfortunately for many teams, UVM's reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future.
- Customization in UVM
This recipe will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. You'll be shown how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. Then we'll cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
- More UVM Registers
This recipe will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.
- Introduction to UVM Registers
The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences and checking results at the register layer. We will also show how to use the UVM Register Layer as a standalone package with OVM 2.1.2.
- Protocol Layering
Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components and tests. This session will show how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
- OVM to UVM Migration
A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.