Join Verification Evangelist Tom Fitzpatrick and view the archived April UVM Recipe of the Month - UVM Connect.
Overview:
UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.
In addition - if you are already an Academy Total Access member, get a head start on UVM Connect and download the UVM Connect Kit.
Watch and Learn:
- Review the principles of the TLM1 and TLM2 standards, including the basic port/export/interface connections in both SystemC and SystemVerilog.
- How to establish TLM-based connections between SystemC and SystemVerilog UVM components.
- How to write converters to transfer transaction data across the language boundary.
- How to wrap a SystemC reference model for use as a SystemVerilog UVM verification component.
- How to access and control key aspects of UVM simulation from SystemC.
* Registration is fulfilled on Mentor.com
Academy Total Access users can download the video recording, and the slides.