Registration is open for a Transforming Verification Seminar on Tuesday, October 23rd in Austin, TX.
Overview:
The challenges of verification continue growing exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that deliver 10-100x advances in verification are required.
This seminar will be held at the Driskill Hotel in Austin with a Keynote Session presented by Harry Foster, Verification Academy Lead Subject Matter Expert & Chief Scientist Verification for Mentor Graphics DVT. Continental breakfast and a buffet lunch will be provided.
Attendees Will Learn:
- How to close the loop between verification plans and verification using electronic closure to ensure you hit your market windows on schedule.
- How to reduce the volume of data within the process while still having full visibility into the progress of the project.
- How to jumpstart the debug process by analyzing results across multiple tool runs.
- How to achieve your targeted functional coverage 10x to 100x times faster.
- How to ensure that each and every test sequence generated has a purpose.
- How to extend coverage capability across an entire simulation server farm.
- The design functions correctly with power always on.
- The power management architecture is correct.
- Each block/power domain can power up/down and reset/restore on power up.
- The HW is generating correct control signals in the correct sequence.
- The full system including HW and SW for power control is functioning correctly.
- How Clock domain crossing (CDC) verification can eliminate the risk of metastability issues in silicon.
- How Automatic formal checks for push-button checking find functional issues without writing a testbench or assertions.
- Formal code coverage closure to prune unreachable bins from the coverage model.
- Connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections.
Date, Time and Location:
- Tuesday, October 23rd
- 8:30 AM - 3:30 AM US/CEntral
- The Driskill - Austin, TX
Learn more and register for this seminar.
* Registration is fulfilled on Mentor.com