Please join Mentor Graphics and register for the FPGA Verification Automation with Mentor VIP web seminar on Wednesday, July 31st at 7:00 AM GMT and 11:00 AM US/Pacific.
Overview:
Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Verification teams are using multiple tools and methodologies to achieve design functionality. One very common and valuable tool is Verification IP. Mentor Graphics VIP provides comprehensive protocol test stimulus and coverage checking that allows you to easily deploy advanced verification methodologies. Verification planning, constrained random and functional coverage methodologies are all included for standard bus protocols, in this case PCIe.
This web seminar will focus on PCIe which is one of the most commonly used protocols and also one of the most complicated.
Date and Time:
- Wednesday, July 31st
- 7:00 AM GMT | 11:00 AM US/Pacific
Watch and Learn:
- Learn how Mentor VIP is the best solution for difficult verification tasks.
- Learn why Mentor VIP is the easiest solution for adopting verification automation for any FPGA team with standard protocols.
Register for this web seminar.