Are you an ASIC/IC, FPGA, Verification Engineer or Manager attending DAC 2017 in Austin?
Be sure to join us June 19th, 20th and 21st in the Verification Academy Booth #429 on the DAC exhibit floor where we will be digging deeper into the challenges of IC Design and Verification with presentations and lively conversation.
Theater sessions include:
- A Fresh Look at UVM and the New UVM Cookbook
- UVM Message Display Commands - Capabilities, Proper Usage and Guidelines
- SystemVerilog Object Oriented Programing Basics used in UVM Verification
- Portable Stimulus is Here! (Almost)
- Accelerating UVM-based Verification from Simulation to Emulation
- Applying Big Data Analytics to Today's Functional Verification Challenge
- Debugging Trends, Challenges, and Novel Solutions
- Staying Competitive by Evolving your FPGA Verification Methodologies
- How Formal Reduces Fault Analysis for ISO 26262
- Formal Verification - Come on Man, Go For It!
- Add Unit Testing to Your Verification Toolbelt
- And more!
Learn more and view the entire session schedule, then register.