April UVM Cookbook Recipe: Advanced UVM Debugging

Join Academy Subject Matter Expert, Tom Fitzpatrick for the April UVM Recipe of the Month - Advanced UVM Debug.

Overview:
As designs continue to grow in complexity, the testbenches to verify those designs are growing right along with them. A recent study shows that, on average, verification engineers spend more time on debug than on any other task, including creating and running the tests. The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.

In addition - if you are already an Academy Full Access member, get a head start with Debug in the UVM Cookbook.

Watch and Learn:
  • How to debug common problems with the UVM configuration database.
  • How to see what types the factory has created for certain components.
  • How to visualize and analyze transactions as waveforms.
  • How to call UVM methods from the command-line to aid in information gathering.
  • How to create, manage and analyze UVM messages to aid in debug.

View Advanced UVM Debug.