Register for DAC 2012 and join us in the Verification Academy Booth #1514 for user and partner presentations, UVM applications, daily technical discussions with Harry Foster and other prominent Verification experts and our Tuesday, June 5th cocktail reception.
Monday, June 4th
10:00 - Simulation and Formal Assertion-Based Verification
11:00 - Bringing UVM to Life
2:00 - Verification of Low Power SoCs with IEEE UPF
3:00 - Evolving Trends in Functional Verification
4:00 - An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
5:00 - Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
Tuesday, June 5th
9:30 - Using the UVM Register Layer
10:00 - Generating Coverage Models and Achieving Coverage Closure
11:00 - Altera Case Study - Using Intelligent Testbench Automation to Verify a Bus Fabric
1:00 - SystemVerilog Tricks for Design & Verification
2:00 - Bringing UVM to Life
3:00 - Evolving Trends in Functional Verification
5:00 - Meet the Verification Experts Cocktail Reception
Wednesday, June 6th
10:00 - Bringing UVM to Life
11:00 - Resistance is Futile: Learning to love UVM!
1:00 - Trends in Full SoC Verification using Emulation
2:00 - Automating Assertion Based Verification with NextOp and Mentor Graphics
3:00 - UVM Express
4:00 - Evolving Trends in Functional Verification
5:00 -THALES ALENIA SPACE Toulouse ASIC&FPGA Verification Flow
Learn more and view the Booth Presentation Schedule