Verify a timing requirement in VHDLtestbench

SystemVerilog
1

There is a signal btl_out which is generated every 20 ms in the design. I have to verify this timing requirement pasted below.

“btl_out clock to output shall(1) be in the following range [ 4ns ; 9ns ] relative to clkrf clock. Can u please tell me how can I verify it in VHDL testbench?

2

In reply to Ashwini Dongre:

You can use SystemVerilog Assertions (SVA) to check this temporaö behavior.
A SVA checker can be connected to a VHDL Testbench using the SystemVerilog bind construct.

3

In reply to chr_sue:

We are not allowed to use system Verilog. We have to write everything in VHDL

4

In reply to Ashwini Dongre:

You need to write behavioral code to do this directly in VHDL, or find some library of checkers.