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  • 2 answers

    How do we check analog signals with respect to a clock

    Hello All,

    I'm writing SVA for a module and I ran across a Analog signal. The problem in hand is,

    the Vdd of the module rises from 0.2V to 1.8V in time 'tr'. The clock associated with the module is clk. Now I need to write an assertion to check if tr < (some constant time value mentioned in the specification).

    How do I do this? If I cant write an assertion, is there any other way I can check this signal? Can I create events at Vdd = 0.2 and Vdd=1.8 and measure the times (not sure just presenting my ideas).

    Thanks for the help.

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    Last Activity 5 months 1 week ago by ajeetha
  • 1 answer

    How to compare schematic results with vhdl analog model results in ADE L tool

    I am trying to compare my analog models which is done in vhdl with spice simulations of the same analog model in ADE L tool.

    I mean top level validation results and analog model results at transistor level(spice simulations)just want to compare the results for checking functionality functionality of the block when modelled in vhdl resembles as same functionality with schematic.

    I know there is simcompare option in the tool, but exactly dont know how to do it.
    any help will be greatly appreciated.


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    Last Activity 1 year 2 months ago by Garcia Sabiro Serge
  • 1 answer

    AMS versus RNM


    What is the main advantage of real number modeling (RNM) over AMS (verilog or VHDL) modeling?
    what are the differences in terms of simulator performance?

    Thank you in advance!!

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    Last Activity 1 year 6 months ago by Ahmed Eisawy
  • 1 answer

    AMS behavioral modeling , a top-down or bottom-up approach?


    I am writing my master thesis on mixed signal verification approaches. I need to resolve a doubt on this issue. When designing an analog circuit which approach is more popular or lets say industry standard:

    1- First to write a behavioral model of the design in one of AMS languages, verify the behaviora functionality of it . Then to design sub-blocks of the design to transistor-level and simulate them using SPICE level simulators.(top down approach?)


    2- First to design in transistor-level and simulate it using SPICE level simulators. Only when the design correct functionality has been proved, trying to simulate using bahevioral models at chip level verification.(bottom up approach)

    thanks in advance !

    p.s I actually know about the benefits of top-down approach but still need to know what could be the benefits of bottom-up approach.

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    Last Activity 1 year 9 months ago by Ahmed Eisawy
  • 0 answers

    AMS Forum + 3 New Course Modules

    1 year 10 months ago - No activity yet