- 1 answer39 views
My requirement is to develop macro which takes cmd list and wait
for each response and other features too. We decided to have macro. so below
is code(not complete but enough to show my problem).
my problem is when i call my_macro in fork join with two different cmd list.due to single handle construction every time, last update override the 1st thread updates.
Is it possible to create different object every time i call macro so that i have two cmd list for each thread of fork.
i tried to create the array of handle but its difficult to get index of each macro.
I tried to mimic this problem in below code please let me know if you need any other update.
PS : I am using OVM methodology
Mimic code is avaliable in http://www.edaplayground.com/x/BHuLast Activity 3 hours 14 min ago by dave_59
- 1 solution1,743 views
I would like to access a DUT signal from within one of my UVM test cases.
But when I try to do so, I get the Cadence ncvlog error E*ILLHIN: illegal location for a hierarchical name (in a package).
This is the organization of the files for compilation.
PRJ_pkg.sv:Last Activity 4 hours 16 min ago by jamesq2001
- 0 answers27 views
I get the following error when running the sequence uvm_reg_bit_bash_seq
UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175): rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 0 in bit #0 of register "spi_rm.reg_0x0" with initial value 'h0000000000000001 yielded 'h0000000000000000 instead of 'h0000000000000001
The message states a correct action, writing 0 in bit #0 with initial value 'h01 yielded 'h00. So why does the sequence expect the value to be 'h01 instead of the correct one, which is 'h00 ?
ThanksLast Activity 8 hours 17 min ago by Mustafa
- 1 answer54 views
We have uvm_resource_db for setting and getting the resource. Uvm have "get_by_name", "get_by_type", "read_by_name", "read_by_type" functions for getting the resource.
please let me know why do we need multiple function for getting the resource or what are the scenarios where we need these different function for getting the resource.
Rahul KumarLast Activity 10 hours 44 min ago by rahulkumarkhokh...
- 1 answer37 views
What is the need of Constraint solver? What will be the difference if i am using below code without line "solve x before y".
rand bit x;
rand bit [1:0]y;
solve x before y;
endclassLast Activity 11 hours 17 min ago by Vinay Jain
- 1 answer6,471 views
I am currently working with UVM RAL and I encountered this error:
"Response queue overflow, response is dropped"
Got the above error since my driver was calling seq_item_port.item_done(rsp). The error however goes when I change it to seq_item_port.item_done() in the driver.
My UVM RAL sequence doesn't explicitly make a call to get_response(rsp) but the register reads and writes work perfectly. My question is,how does RAL sequence get the response back if we don't call the get_response() explicitly?
Thanks!Last Activity 14 hours 31 min ago by jln
- 1 answer1,130 views
In my case, I have a packet in monitor need to be sent to scoreboard and in the scoreboard, I would send the packet into different tlm_analysis_fifos depends on the content of the packet.
I am confused which ports should I use in this path on each boundary and how to connect them together. I checked the scoreboard in the cookbook, it only shows how to connect the analysis port directory the analysis export to the FIFO which is not suitable for my case.
Thanks.Last Activity 16 hours 19 sec ago by nickbayshore
- 0 answers23 views
I've run into an issue where my sequence stops sending new items to the driver. From instrumenting the code it looks like the driver has called item_done(), but nothing happens in the sequencer past the finish_item call. The simplified code in question is :
Driver run_phase :1 day 1 hour ago - No activity yet
- 1 answer122 views
I am getting started with System Verilog. So far I am good with the theoretical concepts. But I want to gain hands on coding experience on system verilog, assertions and coverage. Please suggest me a way to achieve this.
Thanks in advance
-MadhaviLast Activity 19 hours 11 min ago by aprakas7
- 1 answer66 views
I need to execute SV LRM examples.Student/evaluation version of some simulators doesnt support constraint solvers.
Can you please suggest any sites or software by which I can run SV code.
Thanks in advanceLast Activity 19 hours 17 min ago by aprakas7
- 1 answer67 views
I am an m.tech student doing verification of AMBA APB with memory controller as slave .I have made memory controller with APB protocol as DUT and built a plain SV testbench environment with driver acting as master .While doing multiple write and read(writing different data at same address and reading latest data) ,multiple write is happening correctly ,but read data remains at x(don't care).how could I debug this ?Last Activity 19 hours 27 min ago by aprakas7
- 0 answers21 views
ILLHIN illegal location for a hierarchical name(in a package) when accessing testbench top variable to uvm sequence
if (!$value$plusargs("DIRNAME=%s", dir_name)
uvm_report_info("CHECK_DIR",$psprintf("No $value$plusarg +DIRNAME passed in."), UVM_HIGH);
uvm_report_info("CHECK_DIR",$psprintf("Received $value$plusarg +DIRNAME."), UVM_HIGH);
class file_seq extends uvm_sequence #(file_uvc_transaction);
function new(string name="file_seq");
// Sequence body definition
virtual task body();
uvm_report_info("CHECK_DIR",$psprintf("Received $value$plusarg +DIRNAME=%0s. in seq lib", top.dir_name), UVM_NONE);
irun command line : irun +DIRNAME=/home/xx
The compile error is on (E), illegal location for a hierarchical name(in a package). I've tried with $root, no luck.1 day 2 hours ago - No activity yet
- 1 solution133 views
I'm looking for a efficient way to instantiate a lot of signals with similar names. For example, I have 20 signals with the name "switch_0", "switch_1" ... "switch_19". I don't want to have to replicate the names everytime I need to use it.
Can you help me?
When I was using Specman E I could use "switch: list of simple_ports" (or something like that) to instantiate and work with a large number of signals.
lucaLast Activity 1 day 16 hours ago by Avdhut Patel