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  • 1 answer
    39 views

    Create different handle of class in the macro based on number of times macro is called.

    My requirement is to develop macro which takes cmd list and wait
    for each response and other features too. We decided to have macro. so below
    is code(not complete but enough to show my problem).

    Code => http://www.edaplayground.com/x/BHu

    my problem is when i call my_macro in fork join with two different cmd list.due to single handle construction every time, last update override the 1st thread updates.

    Is it possible to create different object every time i call macro so that i have two cmd list for each thread of fork.

    i tried to create the array of handle but its difficult to get index of each macro.

    I tried to mimic this problem in below code please let me know if you need any other update.
    PS : I am using OVM methodology

    Mimic code is avaliable in http://www.edaplayground.com/x/BHu

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    Last Activity 3 hours 14 min ago by dave_59
  • 1 solution
    1,743 views

    How to access a DUT signal from a UVM test case class?

    Hi,

    I would like to access a DUT signal from within one of my UVM test cases.
    But when I try to do so, I get the Cadence ncvlog error E*ILLHIN: illegal location for a hierarchical name (in a package).

    This is the organization of the files for compilation.

    PRJ_pkg.sv:

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    UVM
    Last Activity 4 hours 16 min ago by jamesq2001
  • 0 answers
    88 views

    Infinite Loop using While

    Dear Forum,

    I am getting infite loop when using while statement. And cannot understand why I am getting infinite loop, please help understand:

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    Last Activity 5 hours 33 min ago by cool_cake20
  • 0 answers
    27 views

    UVM register model: strange uvm_error message

    Hello,
    I get the following error when running the sequence uvm_reg_bit_bash_seq
    UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175): rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 0 in bit #0 of register "spi_rm.reg_0x0" with initial value 'h0000000000000001 yielded 'h0000000000000000 instead of 'h0000000000000001

    The message states a correct action, writing 0 in bit #0 with initial value 'h01 yielded 'h00. So why does the sequence expect the value to be 'h01 instead of the correct one, which is 'h00 ?

    Thanks

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    UVM
    Last Activity 8 hours 17 min ago by Mustafa
  • 2 answers
    46 views

    Signedness via parameters

    I have a class:

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    Last Activity 9 hours 38 min ago by shalom
  • 0 answers
    20 views

    array of interface in config_bd

    how to set the array of a interface in config_bd in top module .
    i am using for loop but its giving error ...
    please suugest me ..

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    UVM
    Last Activity 10 hours 12 min ago by cgales
  • 1 answer
    54 views

    uvm_config_db/uvm_resource_db

    Hi All,

    We have uvm_resource_db for setting and getting the resource. Uvm have "get_by_name", "get_by_type", "read_by_name", "read_by_type" functions for getting the resource.

    please let me know why do we need multiple function for getting the resource or what are the scenarios where we need these different function for getting the resource.

    Thanks,
    Rahul Kumar

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    UVM
    Last Activity 10 hours 44 min ago by rahulkumarkhokh...
  • 1 answer
    37 views

    Constraint Solver in SV (Topic: Randomization)

    What is the need of Constraint solver? What will be the difference if i am using below code without line "solve x before y".

    class ABC;
    rand bit x;
    rand bit [1:0]y;
    constraint c
    {
    y inside{[x:3]};
    solve x before y;
    }
    endclass

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    Last Activity 11 hours 17 min ago by Vinay Jain
  • 1 answer
    6,471 views

    get_response() with UVM RAL

    Hi,

    I am currently working with UVM RAL and I encountered this error:
    "Response queue overflow, response is dropped"

    Got the above error since my driver was calling seq_item_port.item_done(rsp). The error however goes when I change it to seq_item_port.item_done() in the driver.

    My UVM RAL sequence doesn't explicitly make a call to get_response(rsp) but the register reads and writes work perfectly. My question is,how does RAL sequence get the response back if we don't call the get_response() explicitly?

    Thanks!

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    UVM
    Last Activity 14 hours 31 min ago by jln
  • 0 answers
    19 views

    RAL_model

    Ral model how to write Front door access code?

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    RAL
    UVM
    15 hours 57 min ago - No activity yet
  • 1 answer
    1,130 views

    How to use tlm_analysis_fifo?

    In my case, I have a packet in monitor need to be sent to scoreboard and in the scoreboard, I would send the packet into different tlm_analysis_fifos depends on the content of the packet.

    I am confused which ports should I use in this path on each boundary and how to connect them together. I checked the scoreboard in the cookbook, it only shows how to connect the analysis port directory the analysis export to the FIFO which is not suitable for my case.

    Thanks.

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    UVM
    Last Activity 16 hours 19 sec ago by nickbayshore
  • 0 answers
    17 views

    UVM Pipelined driver synchronisation

    Hello all,

    I'm currently working on pipelined driver implementation for AHB bus and encountering few issues.

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    UVM
    19 hours 42 min ago - No activity yet
  • 0 answers
    23 views

    Debugging sequence/driver communication

    I've run into an issue where my sequence stops sending new items to the driver. From instrumenting the code it looks like the driver has called item_done(), but nothing happens in the sequencer past the finish_item call. The simplified code in question is :

    Driver run_phase :

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    UVM
    1 day 1 hour ago - No activity yet
  • 1 answer
    122 views

    Coding practices in System Verilog

    Dear all,
    I am getting started with System Verilog. So far I am good with the theoretical concepts. But I want to gain hands on coding experience on system verilog, assertions and coverage. Please suggest me a way to achieve this.
    Thanks in advance
    -Madhavi

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    Last Activity 19 hours 11 min ago by aprakas7
  • 1 answer
    66 views

    System verilog LRM examples execution

    Hi,

    I need to execute SV LRM examples.Student/evaluation version of some simulators doesnt support constraint solvers.
    Can you please suggest any sites or software by which I can run SV code.

    Thanks in advance

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    Last Activity 19 hours 17 min ago by aprakas7
  • 1 answer
    67 views

    AMBA APB verification

    I am an m.tech student doing verification of AMBA APB with memory controller as slave .I have made memory controller with APB protocol as DUT and built a plain SV testbench environment with driver acting as master .While doing multiple write and read(writing different data at same address and reading latest data) ,multiple write is happening correctly ,but read data remains at x(don't care).how could I debug this ?

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    Last Activity 19 hours 27 min ago by aprakas7
  • 0 answers
    21 views

    ILLHIN illegal location for a hierarchical name(in a package) when accessing testbench top variable to uvm sequence

    module top();
    import uvm_pkg::*;
    `include "file_tb_env.sv"

    string dir_name;

    initial begin
    if (!$value$plusargs("DIRNAME=%s", dir_name)
    uvm_report_info("CHECK_DIR",$psprintf("No $value$plusarg +DIRNAME passed in."), UVM_HIGH);
    else
    uvm_report_info("CHECK_DIR",$psprintf("Received $value$plusarg +DIRNAME."), UVM_HIGH);
    end
    endmodule

    class file_seq extends uvm_sequence #(file_uvc_transaction);
    function new(string name="file_seq");
    super.new(name);
    endfunction

    // Sequence body definition
    virtual task body();
    //(E)
    uvm_report_info("CHECK_DIR",$psprintf("Received $value$plusarg +DIRNAME=%0s. in seq lib", top.dir_name), UVM_NONE);
    endtask
    endclass
    irun command line : irun +DIRNAME=/home/xx
    The compile error is on (E), illegal location for a hierarchical name(in a package). I've tried with $root, no luck.

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    UVM
    1 day 2 hours ago - No activity yet
  • 1 solution
    72 views

    To understand the fundaments os SV

    What is the basic difference between Program block and Clocking block. If possible then give example.

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    Last Activity 1 day 12 hours ago by Shalin Mandiwala
  • 1 solution
    133 views

    Coding tip: signals with similar name

    Hi everyone,

    I'm looking for a efficient way to instantiate a lot of signals with similar names. For example, I have 20 signals with the name "switch_0", "switch_1" ... "switch_19". I don't want to have to replicate the names everytime I need to use it.

    Can you help me?

    When I was using Specman E I could use "switch: list of simple_ports" (or something like that) to instantiate and work with a large number of signals.

    Regards,
    luca

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    Last Activity 1 day 16 hours ago by Avdhut Patel