I am running below code in vcs-
module param #(width=16)(a,b,c);
input bit [width:0] a,b;
output bit [width:0] c;
$display("a is %h and b is %h and c is %h and time is %t",a,b,c,$time);
param #(7) p1 (8'ha0,8'h11,c); //line 16
param #(9) p2 (10'h200,10'h14,c); //line 17
output of line 16 and 17 is same. output is a is 000 and b is 000 and c is 000 and time is 0.
Why variable a and b's parametrized widths are not being taken?
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