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  • 1 answer
    17 views

    Callback access through handle/object that is stored in a queue.

    Hi All,

    We access callback function using handle/object, This handle is pushed into queue from top hierarchy.
    As shown in below code.

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    Last Activity 24 sec ago by dave_59
  • 0 answers
    6 views

    uvmc packer max size

    Hello,

    I have a transaction with more than 4k bytes and I try to redefine size (changing from 4096 to 409600) from two files: uvm_pkg.sv and uvmc_common.h.

    - uvm_pkg.sv:38
    `define UVM_PACKER_MAX_BYTES 409600

    - uvmc_common.h:65
    `define UVM_PACKER_MAX_BYTES 409600

    When I try to send a transaction (tlm2 with generic payload using sockets) from sv to sc the size error disappear, but the data received at sc is always zero after 4080 bytes.

    Using:

    - uvmc 2.3.0
    - cadence ius 14.10

    Thanks!

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    UVM
    2 hours 32 min ago - No activity yet
  • 0 answers
    37 views

    Multiple sequencers to a single driver

    Can we able to connect two sequencers to a single driver in an agent?

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    UVM
    Last Activity 3 hours 31 min ago by AndraSocianu_AMIQ
  • 0 answers
    17 views

    UVMC Memory management in systemc

    Hi,

    I have existing SystemC design I am trying to drive from SV side of my uvmc testbench. My problem is such that on SC (design) side of connections it is expected the transactions (tlm_generic_payload) include handle to memory manager (nb_transport_fw, trans.acquire() called on arrival). However, uvmc does not provide such by default.

    I have been trying to redefine converter for generic payload, so I could provide the needed memory manager from converter level (do_unpack). However, everything seems to be static by nature and I have not been able to find a spot where I could add the memory management object in a consistent manner.

    How have you planned the case where design expects memory manager handle from incoming transactions?

    Thanks.

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    UVM
    4 hours 5 min ago - No activity yet
  • 0 answers
    21 views

    UVM FATAL ERROR

    neither the item's sequencer nor dedicated sequencer has been supplied to start item in write_seq uvm fatal error

    -Why these type of errors comes into picture?

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    UVM
    Last Activity 4 hours 57 min ago by cashah85
  • 1 answer
    70 views

    Problem related to connection of two interfaces through configuration.

    Hi All

    I have made BFM for master and slave and all sub component like driver, monitor ,agent of APB and AHB protocol.
    I have made one configuration class of name conifig_AHB_APB in which , I called both interfaces of AHB and APB and declared as Virtual.
    So I want to connect AHB to APB using the above configuration class.
    Tell me how can I connect these both interfaces using config_db, and where this connection can be done in environment or BASE test.
    Actually I have no idea of this type of connection.
    can anyone help me out.........

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    UVM
    Last Activity 5 hours 55 min ago by karandeepsingh
  • 1 answer
    58 views

    virtual sequence

    It is necessary to define separate class of sequencers which is inside the virtual sequence (sequencer handles).or we can use same normal sequencer inside virtual sequence.??

    to get the sequencer which is inside the virtual sequencer, we have create separate agent class or we can set it inside normally create agent (i am trying to verify AND_GATE DUT).

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    UVM
    Last Activity 8 hours 7 min ago by NEHA JAIN
  • 1 answer
    33 views

    Regarding Root access

    Hi,
    For back door access i am using $root in my env. which it shows error like "$root access from within packages is not allowed".
    after that i have added switch "-permissive", now the error is gone.
    Whether the above method is correct or not.

    Thanks,
    Raja

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    UVM
    Last Activity 9 hours 31 min ago by arasupotri.nata...
  • 4 answers
    761 views

    How to resolve vopt-2064 error ?

    Hi,

    I am running a simulation in questasim with following command :
    # vsim +UVM_TESTNAME=test_basic_csr_rdwr_dir +UVM_NO_RELNOTES +uvm_set_action=*,ILLEGALNAME,UVM_WARNING,UVM_NO_ACTION +uvm_set_action=*,UVM_DEPRECATED,UVM_WARNING,UVM_NO_ACTION +uvm_set_action=*,PHASESEQ,UVM_INFO,UVM_NO_ACTION -assertcover -assertdebug -coverage -do "coverage report -file cov_dir/reports/test_basic_csr_rdwr_dir_26513_cov_report;coverage save -onexit cov_dir/coverage/test_basic_csr_rdwr_dir_26513.ucdb; radix -h;set SolveArrayResizeMax 0;run -all; " -l test_basic_csr_rdwr_dir_26513.log -lib WORK -voptargs="+cover=bc+testbench/adc_inst. +acc" -classdebug -solvefaildebug -debugdb -c WORK.testbench

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    Last Activity 9 hours 55 min ago by Dhaval Patel
  • 2 answers
    48 views

    use of struct inside a task

    hello,
    i am writing my UVM scoreboard.
    i want to get device configurations and encapsulate them inside a device_global_cfg_t like so:

    typedef struct {
    bit a;
    bit b;
    bit c;
    bit d;
    int e;
    bit f;
    }device_global_cfg_t;

    when i declare a struct veriable using this typedef:

    virtual task device_actions(tti2fcu_data_c txn);
    fcu_global_cfg_t fcu_global_cfg = get_configurations ();

    // // assign the expected fields of output item
    // // send expected item to cmpr

    endtask : device_actions

    i get the following ERROR:

    0.00 VCS ERROR: SE (fc): Syntax error Following verilog source has syntax error : "yakovy/UVM/SIMULATIONS/Testplan/UL_tests/mem_test/user_link_dir/scoreboard_c.sv", 219: token is 'fcu_global_cfg' fcu_global_cfg_t fcu_global_cfg = get_configurations (); ^ (in ActVCSPostProcess.pm:368)

    any idea why?

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    UVM
    Last Activity 10 hours 1 min ago by kobiyonai
  • 2 answers
    53 views

    Two sequences communication

    I want a sequence(seq1) generating the sequence item A and sending to another sequence(seq2). This sequence(seq2) gets the sequence item A to formed its sequence. How can I do that? Thanks a lot.

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    UVM
    Last Activity 11 hours 31 min ago by karandeepsingh
  • 1 solution
    199 views

    A randomization question between a varible and a value

    Hi there,

    Could anyone explain what's the difference between the following two? Basically why a variable of max_size can't be used instead of an absolute value of 5'h1f? The issue was the xyz in 1) could be still 5'h1f, the intention was to make the random generated data of xyz not equal to its max_size (5'h1f). Thanks!

    1)

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    UVM
    Last Activity 15 hours 15 min ago by nickbayshore
  • 0 answers
    8 views

    how to set the default value of all elements of a queue to zero before we know the length of the queue?

    Hi,
    Is there way to set all the elements that will be accessed in a queue to a default value of say zero? so that when I use the queue I can go ahead and set some bits to 1 later?

    Thanks in advance

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    OVM
    Last Activity 18 hours 23 min ago by dave_59
  • 0 answers
    55 views

    UVM Connect needs wait() before first peek()

    Hi,

    using UVMC 2.3.0 I found out that in order to be able to call peek() on a sc_port tlm_get_peek_if which is onnected to a uvm_tlm_fifo, I need do call wait(1, SC_NS) at the beginning.

    Instead of calling wait I could also do a get() on the same port before calling peek().

    Calling peek() right away using neither wait(1, SC_NS) nor get() causes an error:
    UVM_FATAL /usr/local/uvmc-2.3.0/src/connect/sv/uvmc_tlm1.sv(121) @ 0: reporter [UVMC] Internal error (uvmc_pkg::C2SV_peek): port at id 0 is null

    Has this something to do with the call to wait_connected()
    which is present in function get() in line 216 of file /usr/local/uvmc-2.3.0/src/connect/sc/uvmc_channels.h
    but is not present in function peek() at line 263 of the same file ?

    Can this be patched in UVMC source ?

    Regards,
    Elmar

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    UVM
    Last Activity 19 hours 47 min ago by elmar
  • 1 answer
    32 views

    Interface defination override in instatiation

    I have BFM interaface which is parametrized interface which takes clk and reset as parameter , for ex: interface aa(clk,reset) ,

    But during instantiation , I wan to instantiated it without passing clk and reset as parameter .
    ,for ex : aa a();

    With this I am seeing vcs compile time warnings,bcs of defination mismatches.
    Is there a way to overide interface defination such that my instantiation willnot be shown as vcs compile time warning ?

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    UVM
    Last Activity 23 hours 38 min ago by dave_59
  • 0 answers
    54 views

    Accessing driver function using p_sequencer hierarchy

    HI All,

    UVM Sequencer and driver are connected in uvm agent, Then how can sequence access any function/task of driver using hierarchy "p_sequencer.driver.task()"?

    Where is the p_sequencer in UVM component hierarchy?

    Please reply.

    Thanks,
    Rahul Kumar

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    UVM
    Last Activity 1 day 1 hour ago by caowangyang
  • 0 answers
    43 views

    sprint() issue :data is missing

    Hi All,

    uvm_report_info("AXI_MON",$sformatf("Seen WR Payload data -> %s",mon_pld_req[axi_vif.rmbs_axi_mon_cb.dut_mon_response.wid][0].sprint()),UVM_LOW);

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    UVM
    Last Activity 1 day 6 hours ago by gani
  • 1 answer
    66 views

    Problem related to Task - body in sequence class

    This warning is generated
    UVM_WARNING @ 0: uvm_test_top.env.agent_inst.seqr@@seq_inst [uvm_sequence_base] Body definition undefined

    I am not getting what is problem, please check it

    My sequence Class code------------

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    UVM
    Last Activity 1 day 7 hours ago by NEHA JAIN
  • 2 answers
    91 views

    Assertions

    Hi,

    I am unable to understand the difference between a property and a sequence. Can somebody explain??

    Thankyou

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    Last Activity 2 days 7 min ago by dave_59
  • 2 answers
    58 views

    Accessing base class function using derived class object/handle in systemverilog

    HI All,

    Is there any way to access base class function using derived class object in systemverilog

    Please reply.

    Thanks,
    Rahul Kumar

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    Last Activity 2 days 1 hour ago by Tudor Timi