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  • 0 answers

    Making interface bfm tasks transparent at sequence level


    I have created a BFM-interface with all signals and tasks defined within it.
    The tasks in the bfm are accessible in all the components like drivers and monitors.
    Is there some way where in I can make use of it in the sequences also? Since this does not have the build phase , coz its an object.
    I'm kind of swimming for solutions without having to break it in large scale.

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    Last Activity 3 hours 9 min ago by aming
  • 1 answer

    Failure during loading of systemc compiled object file


    I am facing an issue while trying to load systemc compiled library. Below is the error message i am seeing.
    Could anyone let me know where the issue is ?

    Compiling /tmp/FPGA@suseserver_dpi_17150/linux_x86_64_gcc-4.5.0/exportwrapper.c
    # Loading /tmp/FPGA@suseserver_dpi_17150/linux_x86_64_gcc-4.5.0/
    # Loading /questa_sim/uvm-1.1d/linux_x86_64/
    # Loading /home/FPGA/systemc-2.3.0/lib-linux64/
    # ** Error: (vsim-3197) Load of "/home/FPGA/systemc-2.3.0/lib-linux64/" failed: /home/FPGA/systemc-2.3.0/lib-linux64/ undefined symbol: sc_main.
    # ** Fatal: (vsim-3748) Failed to load DPI object file "/home/FPGA/systemc-2.3.0/lib-linux64/" while trying to resolve 'mti_UVMReMatch'.
    # FATAL ERROR while loading design


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    Last Activity 4 hours 38 min ago by dave_59
  • 0 answers

    Get Following error Field/method name (m_sequencer) not in 'uhdsdi_agent_h'

    I get the following error when i implemented Virstual sequencer and connect it to the Agent

    Field/method name (p_sequencer) not in 'uhdsdi_agent_h'

    I have the following code :

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    9 hours 33 min ago - No activity yet
  • 3 answers

    Is in derived class constructor optional ???

    Hi All,

    I got a unexpected (maybe to me it is strange) result from the fallowing code

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    Last Activity 4 hours 51 min ago by dave_59
  • 0 answers

    How to connect Multiple UVC instans to DUT based on parameter


    I have a DUT having multiple slave interfaces which are controlled by parameter.

    I have created a Master UVC.

    how to instantiate(create object) connect my Master UVC to DUT's slave interfaces based on the parameter .

    In that case how can I handle UVCs monitor analysis port connections with scoreboard based on Parameter


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    6 hours 12 min ago - No activity yet
  • 0 answers

    Facing issue of not getting randomized members in extended class

    My requirement is to randomize the val1 and val2 in base class and use those members in extended class and do multiply,return.

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    Last Activity 6 hours 43 min ago by Bharath_Verif
  • 2 answers

    Dynamic arrays

    hi ,

    The dynamic part of the array must be of unpacked nature. A packed array can not be dynamic ,why?

    Thanks In advaance,

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    Last Activity 8 hours 42 min ago by sivasyammj
  • 0 answers

    DUT signals access in TB

    Hi All,

    There are multiple modules are instantiated in DUT_TOP. I want access signals from different modules in my TB, For this do i need bind all instantiated module separately or is there any other way ?

    Please reply the suggestion.

    Rahul Kumar

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    9 hours 6 min ago - No activity yet
  • 0 answers

    bits assignment w/o loop

    1. I am trying to assign a lot of bits in one assignment in order to avoid loops.
    don't know why it is not compiling...

    data_to_shift = new [Msg_Length*BYTE_WIDTH];
    fcu2dq_expected_bus [mapper_ID][BYTE_WIDTH*shift_offset +: Msg_Length*BYTE_WIDTH] = {data_to_shift};//this giving me the ERROR:

    0.00 VCS ERROR: TCF-CETE (fc): Cannot evaluate the expression, 376 "(Msg_Length * $unit::BYTE_WIDTH)" Cannot evaluate the expression in width of indexed part-select. The expression must be compile time constant.

    // if I assign bit by bit in foreach loop it works:

    foreach (data_to_shift[i])
    fcu2dq_expected_bus [mapper_ID][BYTE_WIDTH*shift_offset+i] = data_to_shift[i];

    2. I am also facing a problem when trying to concatenate two arrays like so:
    data_to_shift = {payload,MC_byte};

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    Last Activity 9 hours 12 min ago by ClaudiaIancu_AMIQ
  • 1 answer

    Transaction Recording - Creating custom streams Questa 10.1b UVM 1.1

    Goal: I would like to get transaction recording in Questa 10.1b to work in a useful way. I want to create a transaction stream for every UVM Monitor I instantiate and be able to add it to my wave by clicking through the hierarchy in the structure window, ie:

    ( and then click on it's stream in the object window)

    - I am using the pre-compiled uvm version that came with Questasim
    - I pass -uvmcontrol=all flag into the simulation.
    - I have set recording detail in the top_level test

    Once transactions appear on a sequencer, QuestaSim automatically creates a trStream for each uniquely named transaction which I can add through the structure window. (locate sequencer and select from object window).

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    Last Activity 9 hours 21 min ago by cwidtman
  • 1 answer

    can we run just testbench without DUT?

    Hi all,

    I am running a testbench without DUT, But the interface outputs are connected as inputs to same testbench (like loop). Does this way simulation works or not??.
    Because in my case, Time is not getting advanced, its staying at 0ns all the time and maximum iteration limit ERROR is shown.

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    Last Activity 10 hours 44 min ago by Richard Hamer (...
  • 0 answers

    How to handle delay in the assertion

    Hi ,

    I have written an assertion as following,

    sequence tx_count_package_lenreset_1; // 20-39 Lanes
    @(posedge txclk1)

    Problem facing :

    --> there is an delay after the posedge clock to rise of strobelane1_txactive.
    --> The delay difference is about 10ps from the posedge to the rise of the signal.
    --> So,Because this sequence "tx_count_package_lenreset_1" is never been high.
    --> I am using this sequence in another property which never triggers because of this issue.

    My view : Something like this, //// Compilation error.....
    sequence tx_count_package_lenreset_1; // 20-39 Lanes
    @(posedge txclk1)
    ##10ps; ($rose(strobelane1_txactive));

    --> I would like to know how to handle it.


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    13 hours 3 min ago - No activity yet
  • 1 answer

    Conditional sequence


    I am relatively new to the UVM and I had a question on implementing conditional sequences. I have multiple sequences where I need to conditionally randomize an input based on the current state of the DUT. Currently, the sequences themselves are using cross module references to go into the interface directly to look at those signals. I think this is the wrong way of doing it, and I've found some information on sequence responses, but I'm not sure if this is the way to go either. Any ideas? Thank you very much.

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    Last Activity 13 hours 21 min ago by cwidtman
  • 0 answers

    Log File Prints 'run' phase is ready to proceed to the 'extract' phase

    HI All

    the test runs default sequence from the main_phase and log file prints the below message
    "reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase "
    How can I stop print the above message in log file when the sequence runs from the main_phase instead of run_phase ?

    Note: Whenever default sequence runs from the run_phase it doesn't print the above message


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    13 hours 55 min ago - No activity yet
  • 0 answers

    Eclipse plugin for UVM

    Is there a eclipse plugin for UVM ,if it is then how to integrate it with Questasim,Ncsim or VCS ,

    or if the above tools have inbuilt ide for uvm

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    Last Activity 14 hours 58 min ago by raghav kumar
  • 0 answers


    i am trying to override the seq1 with seq2 using the set_typr_override_by_type but when i run the code the sequence is generating all zeros. can any one please give the solution for this

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    Last Activity 15 hours 13 min ago by georgean
  • 7 answers

    what $sformat()?

    what is the functionality of $sformat() can u please explain about it?

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    Last Activity 15 hours 58 min ago by SHRI12326
  • 1 solution

    Tool similar to `define during run time

    I would like to access members of 2 different classes based on a 'switch'. For e.g.

    reg1.m1.m = 3;
    reg2.m1.m = 3;

    If I try to do something like this :

    if (i=0)
    `define ABC reg1
    elseif (i=1)
    `define ABC reg2

    for (i=0;i<2;i++) begin
    `ABC.m1.m = 3;

    It will not be possible to do the above since macros are just limited till compilation. So, is there any "tool" in SV, which can do my work?

    Thanks in advance

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    Last Activity 1 day 10 hours ago by Jeevan Garlapati
  • 0 answers

    fatal errors in system verilog

    Hi sir/mam
    I have done spi master core compile all file,simulation also done ,but give fatal errors ater run the code ,
    bellow transcript window display given error mentioned ,
    please suggest me

    ** Fatal: (vsim-131) Null instance encountered when dereferencing '/top_env_spi_sv_unit::scoreboard::run/this*.gen_scb'
    # Time: 0 ps Iteration: 1 Process: /top_env_spi_sv_unit::environment::run_env/#FORK#43_ff03d53 File:
    # Fatal error in Task top_env_spi_sv_unit/scoreboard::run at line 21
    # HDL call sequence:
    # Stopped at 21 Task top_env_spi_sv_unit/scoreboard::run
    # called from 43 Task top_env_spi_sv_unit/environment::run_env

    Thanks in advance

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    Last Activity 1 day 12 hours ago by Nishant Kumar
  • 0 answers

    Passing array of PARAMAETERS to class handle in env


    I have PARAMETERIZED AGENT CLASS, whose multiple instances I will take in the environment, I need to pass different PARAMETERS to different agents.
    I have an array of PARAMETERS, which I need to pass in the environment to multiple agents.
    e.g PARAMETER ADDR_WIDTH [2:0] = {32,32,64};
    PARAMETER DATA_WIDTH [2:0] = {32,32,64};
    In env, delaring agent handle
    abc_agent_c (ADDR_WIDTH,DATA_WIDTH) agent_h[]; (typically in env.svh)
    How I can pass array of parameters to a single handle declaration. As I see cannot use genvar/for loop for same.
    Do I have to define multiple agent handles & pass the array e.g abc_agent_c (ADDR_WIDTH[0],DATA_WIDTH[0]) agent_h_1;
    abc_agent_c (ADDR_WIDTH[1],DATA_WIDTH[1]) agent_h_2;
    Or is there some other workaround, please suggest.

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    Last Activity 1 day 13 hours ago by prashant.kaushik