Search form

Main menu

My Account Menu

Ask a Question

Forums: All Topics

View Mode:
  • 1 answer

    How to pass enum declared in uvm_sequence_item, from driver to Monitor

    Hi I need some help , in using uvm_config_db

    here is the TB
    I have declared enum in my transcation

    class test_trans extends uvm_sequence_item;

    typedef enum int {TEST0,TEST1,TEST2} testname_type_enum;



    in driver class I instantiated this uvm_sequence_item
    protected test_trans driver_tr;

    I am using "testname_type_enum" in case statement to figure out what driver should do when based on {TEST1,TEST2,TEST3},
    which I am providing from sequence

    in sequence I am calling

    `uvm_do_with(req, {req.testname_type_enum == test_trans::TEST1;})

    Now I want to Pass the same info from driver to Monitor, so that monitor can perform only the required task needed for TEST1

    what should I write in Driver and Monitor to make it work ?

    please advice,

    Read more →

    Last Activity 2 hours 18 min ago by kumar.ashith
  • 1 answer

    clock generator with intra delay or inter delay?

    Could you clarify which of the following is better for clock generator

    Read more →

    Last Activity 10 hours 23 min ago by dave_59
  • 2 solutions

    parameterized class: specialization

    In C++ template specialization allows you to parameterize a class, but have 'special' cases for particular cases.

    Note: Looking into the SV LRM , they refer to specialziation as just assigning the unique parameters. That it not the meaning of specialization I am talking about here.

    I would like to do for example:

    Read more →

    Last Activity 11 hours 15 min ago by dave_59
  • 1 answer

    elaboration of exprssion (exp) [*0:$] intersect seq

    Hi ,

    could you provide how the through out operator is executed. (exp) [*0:$] intersect seq

    i guess it is divided into two sequences one is (exp) [*0:$]
    and the other one is seq.
    the sequence (exp) [*0:$] is divided into (exp) or (exp ##1 exp) or .....

    after simulation of only (exp)[*1:$],I came to know that if exp is true in the current slot then repetition of expression is not checked from next clock on words. but from the through out operator meaning ,exp should hold true through out the the meaning getting changed due to the context of through out operator.

    and if we use (exp) [*1:$] in the above sequence instead of (exp)[*0:$] what would be the difference.

    Read more →

    Last Activity 11 hours 27 min ago by srbeeram
  • 0 answers

    Passing array of derived type to function expecting array of base type

    It seems SV does not allow passing an array of derived type to a function expecting an array of base type:

    Read more →

    15 hours 8 min ago - No activity yet
  • 1 solution

    OOO Scoreboard Design

    Hello ,

    How can I design OOO Scoreboard based on the following criteria ?

    1. Two input analysis port
    2. One output analysis port.

    Scoreboard matching would be between one input analysis port(winner of arbitration) and output analysis port. How can I control the read and write direction ?
    Is there any advise for this kind of scoreboard ?


    Read more →

    Last Activity 21 hours 40 min ago by kddholak
  • 1 solution

    derive from uvm_object or not?

    In the testbench (but actually outside the agents - i.e. I am not writing about sequence items or so) I could do with a class for a pretty atomic thing. E.g. consider a class for a complex sample with a clip bit or so:

    Read more →

    Last Activity 21 hours 49 min ago by NiLu
  • 1 answer

    SVA Repetition operator [=

    I am trying to implement this check: between two consecutive asserts of signal A separated by any no of clock cycles signal B should be asserted only once. i.e. A cannot be asserted without B received for previous A.
    I tried to use the repetition operator for this [=

    A |-> (B[=1]) ## [1:$] A;

    I've tried to introduce a bug and get this assertion to fire. But not sure if this will work.

    any thoughts ?

    Read more →

    Last Activity 22 hours 43 min ago by
  • 0 answers

    `uvm_info verbosity_level

    Hi all,

    I was going through UVM basic .when I use `uvm_info like below
    `uvm_info("mg", $psprintf("DUT received cmd=%b, addr=%d, data=%d", _if.cmd, _if.addr,, UVM_MEDIUM);
    and run the simul;ation with
    irun -uvm filename +UVM_VERBOSITY=UVM_NONE .I expect this message not to be printed in log based on verbosity from command line.But still it shows in log file .How can I avoid it to be printed in log.


    Read more →

    Last Activity 1 day 16 hours ago by Tudor Timi
  • 1 answer

    UVM pipelined driver implementation


    I have a query regarding pipelined driver implementation.
    In my driver class,

    xyz_seq_item tx;

    task adr_phase();
    //adress phase operations
    xyz_q[id].q.pushback (tx); //Declare a queue here to push back the sequence item after address phase operations are done

    task data_phase();
    xyz_q.q.popfront(tx); //Get the sequence item out of the queue and do the data operations on it
    //data phase operations
    end task

    Now that I have used a fork-join_none , after these tasks are forked off, "seq_item_port.item_done()" is called and the driver can fetch the next sequence item and carry on the data & address phase operations. These get added to the queue and the bus operation continues.

    Could someone please tell me if this implementation is correct ?

    Read more →

    Last Activity 1 day 19 hours ago by Tudor Timi
  • 0 answers

    Predict - keyword

    Hi All,

    I need a small clarification regarding keyword - "predict". And how is it related to set/get keywords ?
    For instance :-
    rd_val = abc_3.BAR_OFFSET101.predict(32'hFFFF_FFFF);
    $display("debug: rd_val is %x", rd_val);

    Upto my understanding,from the above piece of code I am trying to predict the value of rd_val as FFFF_FFFF, please correct me if I am wrong.

    same thing we can do with set/get keywords.

    So how does it makes the difference .
    NOTE : These[predict , set/get] are methods .

    Read more →

    2 days 23 hours ago - No activity yet
  • 0 answers

    uvm_error: Unable to allocate memory of 3548567040

    Hi Dave,

    I am getting a UVM error while running a simple test.

    It prints the following message:

    Error-[GC-CAM] Cannot allocate memory
    Unable to allocate memory of size 3548567040

    It is strange to me that this error is coming on zero simulation time.
    Could you please help me out on this issue.


    Read more →

    Last Activity 2 days 1 hour ago by rajput7767
  • 1 answer

    Encapsulation issue

    Hi All,

    Please help on encapsulation.
    1. I have a simple following code and the behaviour of the code as follow below:
    1.Created local variable in base class and trying to set using method.
    2.Set local variable with 6 and printing same from base class handle and extended class handle. In case of base class handle it is showing proper value but when i call from extended class it is giving 0..

    kindly help on this.

    Here is the program:

    Read more →

    Last Activity 2 days 11 hours ago by dave_59
  • 1 answer

    Exact use case of SystemVerilog virtual functions


    I have been able to grasp to an extent the concept of virtual functions in SystemVerilog. It says "If a function is defined virtual, then the run-time decides the function to be called based on the object type referred / pointed to". But what is the exact use-case or scenario where it will be required in verification? Please do provide me some practical examples that we encounter in our day-to-day work.


    Read more →

    Last Activity 2 days 11 hours ago by dave_59
  • 1 solution

    Extracting field names of a packed struct

    Is there a way to extract the fields of a packed struct type and the order in which the names appear in the struct ?

    Read more →

    Last Activity 2 days 13 hours ago by dave_59
  • 0 answers


    why connect_phase is called in bottom-up order? is there a specific reason for that?

    Read more →

    Last Activity 2 days 14 hours ago by naresh.ramaram
  • 2 answers

    clarify object allocation in sv

    Last Activity 2 days 18 hours ago by kumar.ashith
  • 1 answer

    Ohh ! Ohhhh !! One Physical Register But Two Address Mapped to it !! How to Tackle Such Scenarios inside UVM Reg Model ?

    Hello Folks,

    Have a typical scenario,

    a. Wherein the Design has a physical register but two address mapped to it.
    b. Lets say two address REGA-Address-0x02 and REGB-Address-0x04 mapped to the same physical register.
    c. When you write to register address 0x02-REGA, then the value gets set to the corresponding bit in the physical register.
    d. And When you read either 0x02-REGA or 0x04-REGB, you get the value set.
    e. But then when you write to register address 0x04-REGB, then the value gets cleared in the corresponding bit in the physical register.

    How to take care of such scenario inside the UVM register model ?
    a. Do we need to have separate register inside the UVM reg model to satisfy this behavior or are there any other techniques ?

    Read more →

    Last Activity 2 days 18 hours ago by Tudor Timi
  • 0 answers

    Connecting Specman to UVM

    I want to connect the Specman enviroment with the UVM enviroment.

    In my scenario I have an SPECMAN VIP but the Scoreboard , Coverage Model , Test-cases and Sequences I want to Write in UVM. So here i have VIP of APB bus which is written in SPECMAN but I want to run the test-cases using UVM environment and want to have a scoreboard and coverage model also in UVM.

    SO can it be possible that using UVM enviroment we can drive the Sequences to the Specman VIP from out side and then again get the Data from the VIP (Specman ) and can have a scoreboarding and Covergae in the UVM again.

    Please provide some guidelines for this scenario.

    Thanks & Regards

    Read more →

    Last Activity 2 days 18 hours ago by Tudor Timi
  • 1 answer

    Mixed bit-types in single register

    How can I test a register with multiple bit types (or field types) within the same register? So I have a register with bits 15:8 = read only and bits 7:0 are read/write. So I want to bit-bash this register, but bitbash does not test read only bits?

    Read more →

    Last Activity 2 days 18 hours ago by Tudor Timi