I have some problem compiling below verilog codes:
t[i][CH_BW-1:0] = in0.x[i][START_BIT +: CH_BW];
# ** Fatal: (vsim-3378) Invalid indexed part-select expression: 'x'.
# Time: 0 fs Iteration: 6 Process: :top_tb:top:dtop:my_top:my_core:data_out_ifmux:gen_out:#ALWAYS#84 File:
# Fatal error in Module sig_ifmux at .....
However, if I rewrite it as below, it could compile.
t[i][CH_BW-1:0] = in0.x[i][START_BIT+CH_BW-1:START_BIT];
May I know if this simple verilog slice addressing syntax is supported by Questa or not? If so, is there additional switches I need to include in vlog? I have tried vlog -sv +vlog01compat but doesn't help.
Read more →