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Verification Academy at DAC 2013

The Verification Academy focuses on key aspects of advanced functional verification, including: UVM/OVM, Coverage, Assertion-Based Verification, Verification Management, CDC Verification, Acceleration, FPGA Verification, and more.

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Verification Academy DAC Session Presentations

Verification Today and Tomorrow

Harry Foster, Mentor Graphics

Every two years, Mentor Graphics commissions Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. This presentation reveals the results of this just-completed study—and the observed convergence of SoC design practices toward a common methodology.


UVM: Out of Committee Into Productivity

Tom Fitzpatrick, Mentor Graphics

This session will look at proven applications of UVM to move you from the conceptual to the practical. We will explore how UVM provides the ideal infrastructure for adopting new techniques, tools and technologies to improve your verification effectiveness. In addition, we will show how the advanced technologies in Questa use UVM to expand your verification capabilities in ways you may not have even thought of.


What's New in UPF 2.1?

Erich Marschner, Mentor Graphics

A new revision of UPF, IEEE 1801-2013 UPF, also known as UPF 2.1, has just been approved. UPF 2.1 clarifies and enhances many of the capabilities of UPF 2.0, as well as adding some new features to enable power intent specifications for more complex designs. This session presents an overview of the changes in UPF 2.1 and explains how these refinements and new features will make power intent specification easier.


UPF-Based Verification for Cypress PSOC

Ellie Burns, Mentor Graphics

For Cypress PSOC devices, the lowest possible power consumption with very short design cycles is critical. Validating the power management (multiple power domains, power up/down of individual blocks) early in the design cycle is key. This session describes the Cypress UPF-based methodology using Questa PASim that helped find and debug power bugs at RTL that would have been disastrous late in the design cycle.


Intelligent Tests: Don't be Constrained

Mark Olen, Mentor Graphics

Intelligent verification has proven to achieve coverage goals 10X faster than constrained random testing, but what if you've already written a SystemVerilog testbench? Learn how the latest advances in intelligent testing can now re-use existing constraints and coverage models to achieve coverage 10X faster. Also learn how intelligent testing can generate embedded test programs to verify your SoC at the system level.


Low Power Design Methodology for IP Providers & Power Aware Verification Getting Started with UPF

John Biggs, ARM & Erich Marschner, Mentor Graphics

Power has become a critical design constraint for today's electronic systems. IEEE 1801 Unified Power Format (UPF) enables specification of power intent to drive both verification and implementation of electronic systems. This session introduces UPF concepts and commands for defining the power management architecture of a system and presents methodology for incorporating power intent into IP and systems design.


The New SystemVerilog 2012 Standard

Cliff Cummings, Sunburst Design

SystemVerilog is the mainstay of modern design and verification. Many new language features have been added in the 2012 standard to promote more efficient design and improve verification. Get an update on new features like multiple class interface inheritance, soft constraints, complex coverpoint bin expressions, new discrete real modeling and more!


Coherent Verification of ARM-based SoCs

William Orme, ARM

This session will present some of the verification practices needed for efficient validation and verification of ARM v8 family compute sub-systems. We will explore some practical approaches to verification challenges for reuse, scalability and integrating cache coherency systems and solutions that ARM is enabling through its ARM Connected Community Partners.


Optimizing for Power Efficient Design

Abhishek Ranjan, Calypto

With the explosion of portable electronic devices, designing for low-power is a critical design constraint. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, via automated tools or manually. This session will review how Power Analysis can be done at the RTL level to drive low power optimizations.