Released on March 31st, 2021
To produce a high yield mixed-signal design today, designers need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at advanced nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical and costly. Design teams are forced to adopt extrapolation methods to shorten the verification cycle and meet time to market demands, at the risk of impacting the design yield. In this paper we discuss a novel ‘variation aware mixed signal verification’ methodology which addresses this problem and delivers high-sigma variation coverage.