Mentor Graphics at DVCon US 2015 | Featuring Posters, Papers and more!

Mentor has more than 20 papers and posters being presented during the conference discussing; Coverage, UVM, Verification IP, Debugging, Formal, Metrics Analysis and more!

Hear from Harry Foster and Stephen Bailey on the state of verification past, present and future while examining the results from a recent industry world-wide verification study. The talk will examine how advanced techniques are taking hold in mainstream design and provide insights on the recent convergence of verification solutions to meet today’s growing challenges.

View more interviews, tutorials, papers and poster papers from DVCon US 2015.

Coverage Formal-Based Techniques Planning, Measurement and Analysis UVM - Universal Verification Methodology

Walk

Sessions

From Tightly Coupled (Loosely Bolted) to Verification Convergence!

This featured luncheon from DVCon US 2015 discusses the state of verification past, present and future while examining the results from a recent industry world-wide verification study.

UVM Rapid Adoption: A Practical Subset of UVM

This featured DVCon 2015 session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.

Goldilocks and System Performance Modeling

This paper focuses on the process of verification of a System-on-a-Chip (SoC) consisting of multiple ARM® AMBA® AXI™ bus fabrics with mix of RTL IP and verification IP master and/or slave blocks.

Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization

This paper explores how the use of embedded debug instrumentation in modern FPGA prototype debuggers can meet the emerging need for system-level debug.

Are You Smarter Than Your Testbench? With a Little Work You Can Be

This paper will discuss ways to keep check on the testbench performance and to understand the functionality being implemented and the effectiveness of the tests.

Want a Boost in Your Regression Throughput?

This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors.

The Big Brain Theory: Visualizing SoC Design & Verification Data

This paper describes the challenge of maximizing utilization of the best design/verification tool we possess - our engineering brains.

Coverage Data Exchange is No Robbery... Or Is It?

This paper introduces a method of exchanging data between two-UCIS compliant coverage database systems without the need for inefficient formats like ASCII or XML.

Jump-Start Software-Driven Hardware Verification with a Verification Framework

This paper describes the benefits of having such a framework and proposes key features of a verification framework for software-driven hardware verification.

Successive Refinement: A Methodology for Incremental Specification of Power Intent

In this paper, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system.

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