Verification Academy at DAC 2016 - The booth theater sessions are now available!

The Verification Academy focuses on key aspects of advanced functional verification. At this year's DAC Booth, we've lined up a number of advanced functional verification sessions with industry subject matter experts.

For those of you not able to attend live, we recorded the sessions to make them available to all our members. You will need to login with your Full Access account to view or download the session video recordings and slides.

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Sessions

Get a Head Start on the New UVM Standard

This session will discuss the new version of UVM coming from the IEEE, the changes and how they'll impact current UVM users. We'll also fill you in on the latest happenings in the UVM committee and introduce you to the UVM Framework.

SystemVerilog Assertions - Bind Files & Best Known Practices

In this session you will learn assertion coding guidelines that help reduce assertion coding effort, assertion coding mistakes and assertion coding frustration.

Back to the Stone Ages for Advanced Verification

This session will revisit the importance of techniques like unit testing as highly productive additions to any modern development approach.

UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

In this session, you will learn how to solve the top 10 common UVM bringup issues in areas such as the config_db, the factory, and sequence execution and more.

Verification IP and Memory Models Improve Productivity and Reduce Risk

This session illustrates how many companies are improving their productivity by moving to third-party verification IP and memory models, complete with protocol checks, coverage models, and compliance test suites.

Verification Patterns: An Optimized Reusable Solution

In this session, we introduce the new Verification Academy Patterns Library and present pattern examples that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.

Get Ready for Portable Stimulus

This session will clearly explain what Portable Stimulus is (and what it isn't), how the Portable Stimulus Working Group is tackling the problem, and what the solution is likely to be.

Formal Verification Tips & Tricks for Fun & Profit

In this session you will learn SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, simple tips to setup the analysis for rapidly reaching a solution, and benefiting from "coverage" in a formal context.

Orange is the New Black, Reset Verification is the New CDC

In this session we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.

Debug Data API Update

In this session we'll update you on the current status of the Debug Data API development and projected timeline of support. We will also demonstrate the Debug Data API to create debug applications written in C/C++ running on early prototypes from Mentor and Cadence.

Verifying Safety-Related Systems

In this session, we will be covering the impact of safety standards on requirements: how they need to be defined; how they need to be managed; and how they need to be mapped to tests to demonstrate that they have been implemented correctly.

Using a Chessboard Challenge to Discover Real-world Formal Techniques

In this session, Oski describes formal techniques included case-splitting, symmetry reduction, assume-guarantee and disabling lower proof depths used to solved a chessboard problem.

Specification to Realization flow using ISequenceSpec™ and Questa® inFact

This session will demonstrate how complete verification can be done in an automated manner, saving time while improving quality with the inFact and ISequenceSpec tools.

Fireside Chat Verification Panel

DAC 2016 | Fireside Chat Panel Discussion

Join the Verification Academy Subject Matter Experts as they field questions about UVM, Portable Stimulus, SystemVerilog, Emulation, Testbenches, Standards, Training, High Level Synthesis, Languages and more!

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