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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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      • Functional Safety
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • UVMF - One Bite at a Time
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    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

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      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
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      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Web Seminar: Clock-Domain Crossing Analyses and Verification - June 27th
      • Web Seminar: Accelerate Design-to-revenue in ASIC Developments - July 10th
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • DAC 2016

DAC 2016

The Verification Academy focuses on key aspects of advanced functional verification. At this year's DAC Booth, we've lined up a number of advanced functional verification sessions with industry subject matter experts.

For those of you not able to attend live, we recorded the sessions to make them available to all our members. You will need to login with your Full Access account to view or download the session video recordings and slides.

Need to become a member?

Tom Fitzpatrick
Cliff Cummings
Neil Johnson
Gordon Allan
Mark Olen
Harry Foster
Doug Smith
Joe Hupcey
Russ Klein
Dave Rich
Dr. Mike Bartley
Vigyan Singhal
Anupam Bakshi
Acceleration Design and Verification Languages Coverage Formal-Based Techniques Simulation-Based Techniques UVM - Universal Verification Methodology
Walk

Sessions

Get a Head Start on the New UVM Standard

DAC 2016 | Get a Head Start on the New UVM Standard

This session will discuss the new version of UVM coming from the IEEE, the changes and how they'll impact current UVM users. We'll also fill you in on the latest happenings in the UVM committee and introduce you to the UVM Framework.

SystemVerilog Assertions - Bind Files & Best Known Practices

DAC 2016 | SystemVerilog Assertions - Bind Files & Best Known Practices

In this session you will learn assertion coding guidelines that help reduce assertion coding effort, assertion coding mistakes and assertion coding frustration.

Back to the Stone Ages for Advanced Verification

DAC 2016 | Back to the Stone Ages for Advanced Verification

This session will revisit the importance of techniques like unit testing as highly productive additions to any modern development approach.

UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

DAC 2016 | UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

In this session, you will learn how to solve the top 10 common UVM bringup issues in areas such as the config_db, the factory, and sequence execution and more.

Verification IP and Memory Models Improve Productivity and Reduce Risk

DAC 2016 | Verification IP and Memory Models Improve Productivity and Reduce Risk

This session illustrates how many companies are improving their productivity by moving to third-party verification IP and memory models, complete with protocol checks, coverage models, and compliance test suites.

Verification Patterns: An Optimized Reusable Solution

DAC 2016 | Verification Patterns - An Optimized Reusable Solution

In this session, we introduce the new Verification Academy Patterns Library and present pattern examples that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.

Get Ready for Portable Stimulus

DAC 2016 | Get Ready for Portable Stimulus

This session will clearly explain what Portable Stimulus is (and what it isn't), how the Portable Stimulus Working Group is tackling the problem, and what the solution is likely to be.

Formal Verification Tips & Tricks for Fun & Profit

DAC 2016 | Formal Verification Tips & Tricks for Fun & Profit

In this session you will learn SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, simple tips to setup the analysis for rapidly reaching a solution, and benefiting from "coverage" in a formal context.

Orange is the New Black, Reset Verification is the New CDC

DAC 2016 | Orange is the New Black, Reset Verification is the New CDC

In this session we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.

Various Methods for Debugging Software in Emulation

DAC 2016 | Various Methods for Debugging Software in Emulation

This session covers the various methods provided for debugging software in the context of emulation.

Debug Data API Update

DAC 2016 | Debug Data API Update

In this session we'll update you on the current status of the Debug Data API development and projected timeline of support. We will also demonstrate the Debug Data API to create debug applications written in C/C++ running on early prototypes from Mentor and Cadence.

Verifying Safety-Related Systems

DAC 2016 | Verifying Safety-Related Systems

In this session, we will be covering the impact of safety standards on requirements: how they need to be defined; how they need to be managed; and how they need to be mapped to tests to demonstrate that they have been implemented correctly.

Using a Chessboard Challenge to Discover Real-world Formal Techniques

DAC 2016 | Using a Chessboard Challenge to Discover Real-world Formal Techniques

In this session, Oski describes formal techniques included case-splitting, symmetry reduction, assume-guarantee and disabling lower proof depths used to solved a chessboard problem.

Specification to Realization flow using ISequenceSpec™ and Questa® inFact

DAC 2016 | Specification to Realization flow using ISequenceSpec™ and Questa® inFact

This session will demonstrate how complete verification can be done in an automated manner, saving time while improving quality with the inFact and ISequenceSpec tools.

Fireside Chat Verification Panel

DAC 2016 | Fireside Chat Panel Discussion

Join the Verification Academy Subject Matter Experts as they field questions about UVM, Portable Stimulus, SystemVerilog, Emulation, Testbenches, Standards, Training, High Level Synthesis, Languages and more!

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