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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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      • Introduction to ISO 26262
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      • Assertion-Based Verification
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • OVM Extended to Efficiently Manage Coverage Metrics

OVM Extended to Efficiently Manage Coverage Metrics

WILSONVILLE, Ore., and SAN JOSE, Calif., 25 Feb 2009

Mentor Graphics (Nasdaq: MENT) and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced they have extended the Open Verification Methodology (OVM) to include the Unified Coverage Database (UCDB) application program interface (API) and an XML interchange format. The availability of the UCDB API and complementary XML interchange format documentation will allow verification teams to manage coverage metrics in a multi-tool, multi-vendor verification environment, and represents a step toward a standardized approach to managing coverage metrics.

Coverage metrics are used to quantify verification effectiveness and completeness, and to highlight areas of a design that require additional verification. Coverage metrics come from numerous sources, including simulation, static design checking, functional formal verification, sequential equivalence checking and emulation. Each verification tool creates coverage metrics that may be discrete, overlapping, or subsets of one another. With the UCDB API and the XML interchange format, verification teams are given the building blocks to manage the enormous amount of information generated during the verification process in a consistent manner with greater flexibility, and to tailor data transfer and analysis capabilities best suited to their tool and verification environment.

The Mentor/Cadence® extension to OVM matches their recent donations to the Accellera Unified Coverage Interoperability Standards (UCIS) technical subcommittee. Documentation for both the UCDB API and XML interchange format is available in the Community Contributions area of OVM World (www.ovmworld.org) under the Apache 2.0 license in keeping with OVM license terms. By using the Apache 2.0 license for this functionality, the specifications are available to everyone in the OVM ecosystem, and the Accellera UCIS technical subcommittee can easily access the specifications and any enhancements as it completes the standardization task.

About Open Verification Methodology

The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The OVM and OVM World began in August 2007 as a joint effort by Cadence Design Systems and Mentor Graphics.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million and employs approximately 4,450 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:

Dean Solov
Cadence Design Systems, Inc.
direct: 408-944-7226
dsolov@cadence.com

Carole Thurman
Mentor Graphics
direct: 503.685.4716
carole_thurman@mentor.com

Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

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