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November 2025

MARLUG - 2025
Simulation Nov 19, 2025 Sunil Sahoo Seminar
Don't Let VHDL Debugging Slow You Down! Use Questa One Sim
Simulation Nov 12, 2025 Nicole Munson Webinar
HLV: Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Nov 05, 2025 Vlada Kalinic Webinar

October 2025

Improving Verification Productivity Using Questa One Sim
Simulation Oct 23, 2025 Karim Ameziane Webinar
Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP
Verification IP Oct 15, 2025 Justin Bunnell Webinar
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
Questa Design Solutions Oct 08, 2025 Kirolos Magdy Webinar
Did You Know QuestaSim Supports VHDL-2019?
Simulation Oct 01, 2025 Abdelrahman Tharwat Webinar

July 2025

Generating SystemVerilog Assertion (SVA) Properties with Property Assist
Assertions Jul 16, 2025 Mark Eslinger Webinar

June 2025

Accelerating Functional Coverage with Questa One CX
Coverage Jun 18, 2025 Chris Crile Webinar
Tackling Emerging DFT Verification Challenges with Questa One
Simulation Jun 12, 2025 Jake Wiltgen Webinar

Agentic AI Webinar

Wednesday, Apr 22nd-8:00 AM PDT

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

Press Release

Siemens accelerates integrated circuit design and verification with agentic AI in Questa One

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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