Academy News
Verification Horizons Blog
Knowledge Verification Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.
The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Latest blog post: Dave Rich Featured on EEWeb by Tom Fitzpatrick
Additional blog posts include:
- How Did I Get Here? by Dennis Brophy
- Expanding the Verification Academy! by Harry Foster
- Get on the Fast Track to Advanced Verification with UVM Express by Dave Rich
- Introducing UVM Connect by Tom Fitzpatrick
Dave Rich - Featured Engineer Interview
EE Web Interview.
How did you get into electronics/ engineering and when did you start?
I had a very early start and knew long before I started college that I wanted to be a computer engineer. My dad was an electrical engineer for Grumman, working on the video electronics for Apollo’s Lunar Lander. When I was around 10, he started an audio/visual business where I helped him install and repair AV equipment. I continued with a similar job with our student A/V center in college.
UVM/OVM Recipe of the Month
Web Seminar Series featuring the UVM/OVM Online Cookbook
The UVM/OVM Online Cookbook is an encyclopedia of Verification Methodology and is utilized by Verification Engineers across the globe to stay current with UVM and OVM.
This series of online seminars, will focus on a featured monthly "recipe" guiding users into a deeper understanding of the material.
Web seminar recipes include:
- UVM Debug - Register | May 24, 2012
- UVM Connect - Recording | Slides
- Introducing UVM Express - Recording | Slides
UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be employed, beyond the usual RTL debugging techniques that designers have used for years. Through a combination of coding techniques (as documented in the DVCon 2012 2nd Place Best Paper, “Better Living Through Better Class-Based SystemVerilog Debug”) and the unique debug facilities in the Questa Verification Platform, this online webinar will show you how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment.
UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. Unfortunately for many teams, UVM's reliance on the object-oriented programming (OOP) features of SystemVerilog and advanced features means that the barrier to adoption of UVM is simply too high. UVM Express makes it easier to adopt key pieces of UVM in a much more straightforward manner, while leaving open the opportunity to adopt full UVM in the future.
Upcoming Verification Events
Featured Verification Events in May and June
May 2012:
- Coverage Closure Workshop - Dallas, TX - May 22 | Austin, TX - May 23
As the size and complexity of designs has grown, the importance of coverage metrics and the quantity of verification data that must be tracked throughout the verification process has also grown. Achieving coverage closure has become an increasingly large and time-consuming task. Successfully completing verification of today’s complex designs within aggressive schedules requires more automation and increased visibility into coverage closure process to ensure resources are appropriately focused.
- CDC Verification Workshop - Fremont, CA - May 23
Today's complex, multi-clock designs create new verification challenges that must be addressed to avoid costly respins and endless debug cycles. In particular, interactions between domains with different and often asynchronous clocks demands verification that each clock domain crossing (CDC) works reliably. Traditional simulation does not address CDC verification well, because simulation semantics do not accurately reflect the silicon behavior of signals crossing clock domain boundaries. Targeted verification technology that focuses specifically on the CDC verification problem, using an integrated combination of verification technologies, has become absolutely necessary. This workshop will deliver an overview of Questa CDC followed by a hands-on experience.
Mentor Graphics Launches Next Generation Veloce2 Emulation Platform with VirtuaLAB Capabilities
Press Release.
WILSONVILLE, Ore., April 25, 2012 — Mentor Graphics Corp. (NASDAQ: MENT), a leader in high-performance system verification solutions, today announced the availability of the Veloce®2 platform, the next-generation of emulation solutions for the verification of electronic system and Systems on Chip (SoC) designs. Built to accommodate up to two billion gate designs, the Veloce2 platform delivers twice the performance, twice the capacity and four times productivity gain in the same footprint and power consumption as the first-generation Veloce platform. In addition, a new concept called Veloce VirtuaLAB gives verification engineers access to easy-to-use, software-based peripherals, connected to the Veloce platform, which provide a “virtual lab” environment to verify complex electronics systems including the embedded software and the SoCs that make up the system prior to first silicon availability.
Veloce2 is built upon the totally new, full custom emulation IC, Crystal2, developed from the ground up by Mentor. Delivering fast compile, full debug visibility, and advanced memory modeling, Crystal2 is at the heart of the Veloce2 platform’s performance and capacity gains.
Mentor Graphics Adds MIPI Protocol Verification IP to the Questa Verification IP Library
Press Release.
WILSONVILLE, Ore., April 19, 2012—Mentor Graphics Corporation (NASDAQ: MENT) today announced that Questa® Verification IP (VIP) now supports several MIPI Alliance specifications, including CSI, DSI and the recently announced LLI. As a Contributor Member in MIPI Alliance, Mentor sees the standardization of interfaces targeted for use in mobile devices as a step forward for the industry, decreasing time to market, reducing costs and improving interoperability. With this release of Questa VIP, designers can now rapidly verify the correct interpretation of several MIPI specifications. This allows less time to be spent developing the interface logic, and more time to be spent on the key differentiating functionality within the design.
Questa VIP provides engineers with standard SystemVerilog components for both UVM and OVM using a common architecture for each across all supported protocols.
Mentor Graphics New Questa Platform Functionality Boosts Productivity across the Verification Spectrum
Press Release.
WILSONVILLE, Ore., April 16, 2012 — Mentor Graphics Corp. (NASDAQ: MENT) today announced the 10.1 release of the Questa® functional verification platform, a tightly integrated solution that is transforming the functional verification of complex System-on-Chip (SoC) and FPGA designs. This new release extends Mentor’s technology leadership in verification productivity with increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with the most comprehensive Unified Power Format (UPF) support available.
“The Questa functional verification platform contains an integrated set of leading-edge technologies that address the major verification challenges faced by today’s complex SoC, ASIC, and FPGA designs,” said John Lenyo, vice president and general manager of the Design Verification Technology division of Mentor Graphics. “Design teams are looking for solutions that increase total verification throughput, improve verification quality, speed up adoption of new methodologies and effectively analyze verification results. This release of the Questa platform, combined with our comprehensive Verification Academy website, bring these powerful verification solutions and “know-how” to verification teams around the globe.”
Three Essential Steps to SoC Design and Verification
New article on the Tech Design Forum website by Mark Peryer and Shabtay Matalon.
This article will introduce three ESL-based, software-hardware verification steps.
"One of the major challenges in developing an application platform, such as a mobile tablet, is to ensure that the platform works correctly in all possible modes of operation and that software running on the platform is validated and optimized before the hardware is implemented as RTL...."
Mentor Graphics Drives Broader Adoption of UVM
Press Release.
WILSONVILLE, Ore., February 22, 2012 — Mentor Graphics Corporation (NASDAQ: MENT) today announced expanded support for the Universal Verification Methodology (UVM). The UVM delivers productivity gains made possible by reuse in functional verification. For verification teams with minimal exposure to UVM, the first step to implement a UVM-based verification environment is simply getting started. To facilitate that first step, Mentor introduces UVM Express, a way to progressively adopt a UVM methodology. Other verification teams have an established UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved. For those verification teams, Mentor introduces UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog.
"Mentor continues to see massive interest in UVM, and we are committed to leading the effort to make UVM an integral part of every functional verification flow," said John Lenyo, vice president and general manager of the Design Verification Technology division at Mentor Graphics. "For verification teams using UVM for the first time, UVM Express makes getting started easy and intuitive, and extends rapid productivity gains to a broader scope of design projects. With UVM Connect, we've created a link between abstraction levels that enables design and verification engineers to take advantage of each level's best features without sacrificing the ability to reuse work."