Intelligent Testbench Automation (iTBA)
Achieving coverage closure is consistently identified as one of the most difficult challenges facing electronics product development teams. Over the past few years, the industry’s leading functional verification engineering teams have begun turning to a new and emerging technology called Intelligent Testbench Automation (iTBA). Intelligent Testbench Automation (iTBA) combines the high quality of directed testing with the high quantity of constrained random testing, and can be easily integrated into existing verification environments. This module provides a complete introduction to Intelligent Testbench Automation (iTBA), showing how you can achieve your coverage goals >10X faster, leaving you the option to reduce your verification time, expand your coverage targets even further, or both.
The target audiences for this module include:
- Crawl - content is technical, but at an introductory level, and of interest to novice engineers.
- Walk - content is of general interest, particularly to managers, but also engineers.
- Run - content is technical in nature, and of interest to engineers.
- iTBA Primer
- Introduction to iTBA
- Integrating iTBA into a UVM/OVM Environment
- Integrating iTBA into an Existing Set of Directed Tests
- Integrating iTBA into an ‘e’ Environment
- Integrating iTBA into a SystemC Environment
- Combining Rule Graphs and Constraints
- Distributed Simulation for Even Faster Functional Coverage
- Applications of Configurable Graphs
- Applications of Reactive Graphs
This session provides an overview of Intelligent Testbench Automation, including definitions, concepts, and technical innovations. The concept of automatically generating testbench sequences from a grammar with syntax will be discussed.
This session compares Intelligent Testbench Automation to existing directed test and constrained random test methods, highlighting key differences. It will also describe the basic steps to successfully implement an iTBA component including stimulus description, coverage strategy description, configuration selection, and environment selection. In addition, iTBA test component simulation options are discussed and typical iTBA coverage closure results are shown.
This session describes integrating Intelligent Testbench Automation into a UVM/OVM environment, re-using existing SystemVerilog VIP, and achieving functional coverage >10X faster.
This session describes integrating Intelligent Testbench Automation into a directed test environment, re-using existing directed test code, and achieving >10X more functional coverage.
This session describes integrating Intelligent Testbench Automation into an 'e' environment, re-using existing eVCs, and achieving functional coverage >10X faster.
This session describes integrating Intelligent Testbench Automation into a SystemC environment, re-using existing SystemC VIP, and achieving functional coverage >10X faster.
This session describes integrating algebraic constraints into a graph-based testbench description, making the migration from existing constrained random testing environments even easier. Static constraints, dynamic constraints, coverage constraints, and control constraints will be discussed.
This session describes how Intelligent Testbench Automation can distribute its process across a network of simulation servers, to achieve functional coverage goals even faster. iTBA realizes nearly linear results (i.e. 100 servers achieves better than 95X improvement), as overhead is less than 5%, and no redundant work is performed by each server. Automatic allocation of work, load balancing, and coverage monitoring will also be discussed.
This session describes how configurable graphs can be developed to support broad re-use and to allow stimulus to be easily focused on specific areas without modifying the graph source.
This session describes how graphs can be made dynamically reactive to opportunistically target coverage that depends on testbench or DUT state.